Lines Matching +full:max +full:- +full:output +full:- +full:impedance
1 // SPDX-License-Identifier: GPL-2.0
18 #include <dt-bindings/net/ti-dp83867.h>
184 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
191 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
196 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
197 mac = (u8 *)ndev->dev_addr; in dp83867_set_wol()
200 return -EINVAL; in dp83867_set_wol()
214 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
216 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
218 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83867_set_wol()
220 (wol->sopass[5] << 8) | wol->sopass[4]); in dp83867_set_wol()
227 if (wol->wolopts & WAKE_UCAST) in dp83867_set_wol()
232 if (wol->wolopts & WAKE_BCAST) in dp83867_set_wol()
252 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | in dp83867_get_wol()
254 wol->wolopts = 0; in dp83867_get_wol()
259 wol->wolopts |= WAKE_UCAST; in dp83867_get_wol()
262 wol->wolopts |= WAKE_BCAST; in dp83867_get_wol()
265 wol->wolopts |= WAKE_MAGIC; in dp83867_get_wol()
270 wol->sopass[0] = (sopass_val & 0xff); in dp83867_get_wol()
271 wol->sopass[1] = (sopass_val >> 8); in dp83867_get_wol()
275 wol->sopass[2] = (sopass_val & 0xff); in dp83867_get_wol()
276 wol->sopass[3] = (sopass_val >> 8); in dp83867_get_wol()
280 wol->sopass[4] = (sopass_val & 0xff); in dp83867_get_wol()
281 wol->sopass[5] = (sopass_val >> 8); in dp83867_get_wol()
283 wol->wolopts |= WAKE_MAGICSECURE; in dp83867_get_wol()
287 wol->wolopts = 0; in dp83867_get_wol()
294 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83867_config_intr()
327 phydev->duplex = DUPLEX_FULL; in dp83867_read_status()
329 phydev->duplex = DUPLEX_HALF; in dp83867_read_status()
332 phydev->speed = SPEED_1000; in dp83867_read_status()
334 phydev->speed = SPEED_100; in dp83867_read_status()
336 phydev->speed = SPEED_10; in dp83867_read_status()
366 return -EINVAL; in dp83867_get_downshift()
379 return -E2BIG; in dp83867_set_downshift()
401 return -EINVAL; in dp83867_set_downshift()
415 switch (tuna->id) { in dp83867_get_tunable()
419 return -EOPNOTSUPP; in dp83867_get_tunable()
426 switch (tuna->id) { in dp83867_set_tunable()
430 return -EOPNOTSUPP; in dp83867_set_tunable()
437 (struct dp83867_private *)phydev->priv; in dp83867_config_port_mirroring()
439 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) in dp83867_config_port_mirroring()
450 struct dp83867_private *dp83867 = phydev->priv; in dp83867_verify_rgmii_cfg()
455 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { in dp83867_verify_rgmii_cfg()
466 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" in dp83867_verify_rgmii_cfg()
467 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", in dp83867_verify_rgmii_cfg()
472 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
473 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && in dp83867_verify_rgmii_cfg()
474 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
475 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
476 return -EINVAL; in dp83867_verify_rgmii_cfg()
480 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
481 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && in dp83867_verify_rgmii_cfg()
482 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
483 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
484 return -EINVAL; in dp83867_verify_rgmii_cfg()
493 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
494 struct device *dev = &phydev->mdio.dev; in dp83867_of_init()
495 struct device_node *of_node = dev->of_node; in dp83867_of_init()
499 return -ENODEV; in dp83867_of_init()
502 ret = of_property_read_u32(of_node, "ti,clk-output-sel", in dp83867_of_init()
503 &dp83867->clk_output_sel); in dp83867_of_init()
506 dp83867->set_clk_output = true; in dp83867_of_init()
510 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && in dp83867_of_init()
511 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { in dp83867_of_init()
512 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
513 dp83867->clk_output_sel); in dp83867_of_init()
514 return -EINVAL; in dp83867_of_init()
518 if (of_property_read_bool(of_node, "ti,max-output-impedance")) in dp83867_of_init()
519 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; in dp83867_of_init()
520 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) in dp83867_of_init()
521 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; in dp83867_of_init()
523 dp83867->io_impedance = -1; /* leave at default */ in dp83867_of_init()
525 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, in dp83867_of_init()
526 "ti,dp83867-rxctrl-strap-quirk"); in dp83867_of_init()
528 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, in dp83867_of_init()
529 "ti,sgmii-ref-clock-output-enable"); in dp83867_of_init()
531 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; in dp83867_of_init()
532 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", in dp83867_of_init()
533 &dp83867->rx_id_delay); in dp83867_of_init()
534 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { in dp83867_of_init()
536 "ti,rx-internal-delay value of %u out of range\n", in dp83867_of_init()
537 dp83867->rx_id_delay); in dp83867_of_init()
538 return -EINVAL; in dp83867_of_init()
541 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; in dp83867_of_init()
542 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", in dp83867_of_init()
543 &dp83867->tx_id_delay); in dp83867_of_init()
544 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { in dp83867_of_init()
546 "ti,tx-internal-delay value of %u out of range\n", in dp83867_of_init()
547 dp83867->tx_id_delay); in dp83867_of_init()
548 return -EINVAL; in dp83867_of_init()
551 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) in dp83867_of_init()
552 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; in dp83867_of_init()
554 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) in dp83867_of_init()
555 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; in dp83867_of_init()
557 ret = of_property_read_u32(of_node, "ti,fifo-depth", in dp83867_of_init()
558 &dp83867->tx_fifo_depth); in dp83867_of_init()
560 ret = of_property_read_u32(of_node, "tx-fifo-depth", in dp83867_of_init()
561 &dp83867->tx_fifo_depth); in dp83867_of_init()
563 dp83867->tx_fifo_depth = in dp83867_of_init()
567 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
568 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
569 dp83867->tx_fifo_depth); in dp83867_of_init()
570 return -EINVAL; in dp83867_of_init()
573 ret = of_property_read_u32(of_node, "rx-fifo-depth", in dp83867_of_init()
574 &dp83867->rx_fifo_depth); in dp83867_of_init()
576 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
578 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
579 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
580 dp83867->rx_fifo_depth); in dp83867_of_init()
581 return -EINVAL; in dp83867_of_init()
597 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), in dp83867_probe()
600 return -ENOMEM; in dp83867_probe()
602 phydev->priv = dp83867; in dp83867_probe()
609 struct dp83867_private *dp83867 = phydev->priv; in dp83867_config_init()
624 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
631 * be set to 0x2. This may causes the PHY link to be unstable - in dp83867_config_init()
643 phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
649 val |= (dp83867->tx_fifo_depth << in dp83867_config_init()
652 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
654 val |= (dp83867->rx_fifo_depth << in dp83867_config_init()
696 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in dp83867_config_init()
699 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in dp83867_config_init()
702 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in dp83867_config_init()
708 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) in dp83867_config_init()
709 delay |= dp83867->rx_id_delay; in dp83867_config_init()
710 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) in dp83867_config_init()
711 delay |= dp83867->tx_id_delay << in dp83867_config_init()
718 /* If specified, set io impedance */ in dp83867_config_init()
719 if (dp83867->io_impedance >= 0) in dp83867_config_init()
722 dp83867->io_impedance); in dp83867_config_init()
724 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
751 /* SGMII type is set to 4-wire mode by default. in dp83867_config_init()
753 * switch on 6-wire mode. in dp83867_config_init()
755 if (dp83867->sgmii_ref_clk_en) in dp83867_config_init()
765 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
771 /* Enable Interrupt output INT_OE in CFG3 register */ in dp83867_config_init()
778 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) in dp83867_config_init()
781 /* Clock output selection if muxing property is set */ in dp83867_config_init()
782 if (dp83867->set_clk_output) { in dp83867_config_init()
785 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { in dp83867_config_init()
789 val = dp83867->clk_output_sel << in dp83867_config_init()
819 * hence no new in-band message from PHY to MAC side SGMII. in dp83867_link_change_notify()
822 * SGMII wouldn`t receive new in-band message from TI PHY with in dp83867_link_change_notify()
824 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg in dp83867_link_change_notify()
827 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_link_change_notify()