xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
7*4882a593Smuzhiyun#include "rk3399.dtsi"
8*4882a593Smuzhiyun#include "rk3399-opp.dtsi"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	leds {
12*4882a593Smuzhiyun		compatible = "gpio-leds";
13*4882a593Smuzhiyun		pinctrl-names = "default";
14*4882a593Smuzhiyun		pinctrl-0 = <&module_led_pin>;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun		module_led: led-0 {
17*4882a593Smuzhiyun			label = "module_led";
18*4882a593Smuzhiyun			gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
19*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
20*4882a593Smuzhiyun			panic-indicator;
21*4882a593Smuzhiyun		};
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	/*
25*4882a593Smuzhiyun	 * Overwrite the opp-table for CPUB as this board uses a different
26*4882a593Smuzhiyun	 * regulator (FAN53555) that only allows 10mV steps and therefore
27*4882a593Smuzhiyun	 * can't reach the operation point target voltages from rk3399-opp.dtsi
28*4882a593Smuzhiyun	 */
29*4882a593Smuzhiyun	/delete-node/ opp-table1;
30*4882a593Smuzhiyun	cluster1_opp: opp-table1 {
31*4882a593Smuzhiyun		compatible = "operating-points-v2";
32*4882a593Smuzhiyun		opp-shared;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun		opp00 {
35*4882a593Smuzhiyun			opp-hz = /bits/ 64 <408000000>;
36*4882a593Smuzhiyun			opp-microvolt = <800000>;
37*4882a593Smuzhiyun			clock-latency-ns = <40000>;
38*4882a593Smuzhiyun		};
39*4882a593Smuzhiyun		opp01 {
40*4882a593Smuzhiyun			opp-hz = /bits/ 64 <600000000>;
41*4882a593Smuzhiyun			opp-microvolt = <800000>;
42*4882a593Smuzhiyun		};
43*4882a593Smuzhiyun		opp02 {
44*4882a593Smuzhiyun			opp-hz = /bits/ 64 <816000000>;
45*4882a593Smuzhiyun			opp-microvolt = <830000>;
46*4882a593Smuzhiyun			opp-suspend;
47*4882a593Smuzhiyun		};
48*4882a593Smuzhiyun		opp03 {
49*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1008000000>;
50*4882a593Smuzhiyun			opp-microvolt = <880000>;
51*4882a593Smuzhiyun		};
52*4882a593Smuzhiyun		opp04 {
53*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1200000000>;
54*4882a593Smuzhiyun			opp-microvolt = <950000>;
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun		opp05 {
57*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1416000000>;
58*4882a593Smuzhiyun			opp-microvolt = <1030000>;
59*4882a593Smuzhiyun		};
60*4882a593Smuzhiyun		opp06 {
61*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1608000000>;
62*4882a593Smuzhiyun			opp-microvolt = <1100000>;
63*4882a593Smuzhiyun		};
64*4882a593Smuzhiyun		opp07 {
65*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1800000000>;
66*4882a593Smuzhiyun			opp-microvolt = <1200000>;
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun		opp08 {
69*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1992000000>;
70*4882a593Smuzhiyun			opp-microvolt = <1230000>;
71*4882a593Smuzhiyun			turbo-mode;
72*4882a593Smuzhiyun		};
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun	clkin_gmac: external-gmac-clock {
76*4882a593Smuzhiyun		compatible = "fixed-clock";
77*4882a593Smuzhiyun		clock-frequency = <125000000>;
78*4882a593Smuzhiyun		clock-output-names = "clkin_gmac";
79*4882a593Smuzhiyun		#clock-cells = <0>;
80*4882a593Smuzhiyun	};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	vcc1v2_phy: vcc1v2-phy {
83*4882a593Smuzhiyun		compatible = "regulator-fixed";
84*4882a593Smuzhiyun		regulator-name = "vcc1v2_phy";
85*4882a593Smuzhiyun		regulator-always-on;
86*4882a593Smuzhiyun		regulator-boot-on;
87*4882a593Smuzhiyun		regulator-min-microvolt = <1200000>;
88*4882a593Smuzhiyun		regulator-max-microvolt = <1200000>;
89*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
90*4882a593Smuzhiyun	};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun	vcc3v3_sys: vcc3v3-sys {
93*4882a593Smuzhiyun		compatible = "regulator-fixed";
94*4882a593Smuzhiyun		regulator-name = "vcc3v3_sys";
95*4882a593Smuzhiyun		regulator-always-on;
96*4882a593Smuzhiyun		regulator-boot-on;
97*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
98*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
99*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
100*4882a593Smuzhiyun	};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host-regulator {
103*4882a593Smuzhiyun		compatible = "regulator-fixed";
104*4882a593Smuzhiyun		gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
105*4882a593Smuzhiyun		pinctrl-names = "default";
106*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en>;
107*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
108*4882a593Smuzhiyun		regulator-always-on;
109*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
110*4882a593Smuzhiyun	};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun	vcc5v0_sys: vcc5v0-sys {
113*4882a593Smuzhiyun		compatible = "regulator-fixed";
114*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
115*4882a593Smuzhiyun		regulator-always-on;
116*4882a593Smuzhiyun		regulator-boot-on;
117*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
118*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun&cpu_b0 {
123*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_b>;
124*4882a593Smuzhiyun};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun&cpu_b1 {
127*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_b>;
128*4882a593Smuzhiyun};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun&cpu_l0 {
131*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
132*4882a593Smuzhiyun};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun&cpu_l1 {
135*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
136*4882a593Smuzhiyun};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun&cpu_l2 {
139*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
140*4882a593Smuzhiyun};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun&cpu_l3 {
143*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
144*4882a593Smuzhiyun};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun&emmc_phy {
147*4882a593Smuzhiyun	status = "okay";
148*4882a593Smuzhiyun	drive-impedance-ohm = <33>;
149*4882a593Smuzhiyun};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun&gmac {
152*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_RMII_SRC>;
153*4882a593Smuzhiyun	assigned-clock-parents = <&clkin_gmac>;
154*4882a593Smuzhiyun	clock_in_out = "input";
155*4882a593Smuzhiyun	phy-supply = <&vcc1v2_phy>;
156*4882a593Smuzhiyun	phy-mode = "rgmii";
157*4882a593Smuzhiyun	pinctrl-names = "default";
158*4882a593Smuzhiyun	pinctrl-0 = <&rgmii_pins>;
159*4882a593Smuzhiyun	snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
160*4882a593Smuzhiyun	snps,reset-active-low;
161*4882a593Smuzhiyun	snps,reset-delays-us = <0 10000 50000>;
162*4882a593Smuzhiyun	tx_delay = <0x10>;
163*4882a593Smuzhiyun	rx_delay = <0x10>;
164*4882a593Smuzhiyun	status = "okay";
165*4882a593Smuzhiyun};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun&gpu {
168*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
169*4882a593Smuzhiyun	status = "okay";
170*4882a593Smuzhiyun};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun&i2c0 {
173*4882a593Smuzhiyun	status = "okay";
174*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <168>;
175*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <4>;
176*4882a593Smuzhiyun	clock-frequency = <400000>;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun	rk808: pmic@1b {
179*4882a593Smuzhiyun		compatible = "rockchip,rk808";
180*4882a593Smuzhiyun		reg = <0x1b>;
181*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
182*4882a593Smuzhiyun		interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
183*4882a593Smuzhiyun		#clock-cells = <1>;
184*4882a593Smuzhiyun		clock-output-names = "xin32k", "rk808-clkout2";
185*4882a593Smuzhiyun		pinctrl-names = "default";
186*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int_l>;
187*4882a593Smuzhiyun		rockchip,system-power-controller;
188*4882a593Smuzhiyun		wakeup-source;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun		vcc1-supply = <&vcc5v0_sys>;
191*4882a593Smuzhiyun		vcc2-supply = <&vcc5v0_sys>;
192*4882a593Smuzhiyun		vcc3-supply = <&vcc5v0_sys>;
193*4882a593Smuzhiyun		vcc4-supply = <&vcc5v0_sys>;
194*4882a593Smuzhiyun		vcc6-supply = <&vcc5v0_sys>;
195*4882a593Smuzhiyun		vcc7-supply = <&vcc5v0_sys>;
196*4882a593Smuzhiyun		vcc8-supply = <&vcc3v3_sys>;
197*4882a593Smuzhiyun		vcc9-supply = <&vcc5v0_sys>;
198*4882a593Smuzhiyun		vcc10-supply = <&vcc5v0_sys>;
199*4882a593Smuzhiyun		vcc11-supply = <&vcc5v0_sys>;
200*4882a593Smuzhiyun		vcc12-supply = <&vcc3v3_sys>;
201*4882a593Smuzhiyun		vddio-supply = <&vcc1v8_pmu>;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun		regulators {
204*4882a593Smuzhiyun			vdd_center: DCDC_REG1 {
205*4882a593Smuzhiyun				regulator-name = "vdd_center";
206*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
207*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
208*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
209*4882a593Smuzhiyun				regulator-always-on;
210*4882a593Smuzhiyun				regulator-boot-on;
211*4882a593Smuzhiyun				regulator-state-mem {
212*4882a593Smuzhiyun					regulator-off-in-suspend;
213*4882a593Smuzhiyun				};
214*4882a593Smuzhiyun			};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun			vdd_cpu_l: DCDC_REG2 {
217*4882a593Smuzhiyun				regulator-name = "vdd_cpu_l";
218*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
219*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
220*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
221*4882a593Smuzhiyun				regulator-always-on;
222*4882a593Smuzhiyun				regulator-boot-on;
223*4882a593Smuzhiyun				regulator-state-mem {
224*4882a593Smuzhiyun					regulator-off-in-suspend;
225*4882a593Smuzhiyun				};
226*4882a593Smuzhiyun			};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
229*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
230*4882a593Smuzhiyun				regulator-always-on;
231*4882a593Smuzhiyun				regulator-boot-on;
232*4882a593Smuzhiyun				regulator-state-mem {
233*4882a593Smuzhiyun					regulator-on-in-suspend;
234*4882a593Smuzhiyun				};
235*4882a593Smuzhiyun			};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun			vcc_1v8: DCDC_REG4 {
238*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
239*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
240*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
241*4882a593Smuzhiyun				regulator-always-on;
242*4882a593Smuzhiyun				regulator-boot-on;
243*4882a593Smuzhiyun				regulator-state-mem {
244*4882a593Smuzhiyun					regulator-on-in-suspend;
245*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
246*4882a593Smuzhiyun				};
247*4882a593Smuzhiyun			};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun			vcc_ldo1: LDO_REG1 {
250*4882a593Smuzhiyun				regulator-name = "vcc_ldo1";
251*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
252*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
253*4882a593Smuzhiyun				regulator-boot-on;
254*4882a593Smuzhiyun				regulator-state-mem {
255*4882a593Smuzhiyun					regulator-off-in-suspend;
256*4882a593Smuzhiyun				};
257*4882a593Smuzhiyun			};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun			vcc1v8_hdmi: LDO_REG2 {
260*4882a593Smuzhiyun				regulator-name = "vcc1v8_hdmi";
261*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
262*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
263*4882a593Smuzhiyun				regulator-always-on;
264*4882a593Smuzhiyun				regulator-boot-on;
265*4882a593Smuzhiyun				regulator-state-mem {
266*4882a593Smuzhiyun					regulator-off-in-suspend;
267*4882a593Smuzhiyun				};
268*4882a593Smuzhiyun			};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun			vcc1v8_pmu: LDO_REG3 {
271*4882a593Smuzhiyun				regulator-name = "vcc1v8_pmu";
272*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
273*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
274*4882a593Smuzhiyun				regulator-always-on;
275*4882a593Smuzhiyun				regulator-boot-on;
276*4882a593Smuzhiyun				regulator-state-mem {
277*4882a593Smuzhiyun					regulator-on-in-suspend;
278*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
279*4882a593Smuzhiyun				};
280*4882a593Smuzhiyun			};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun			vcc_sd: LDO_REG4 {
283*4882a593Smuzhiyun				regulator-name = "vcc_sd";
284*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
285*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
286*4882a593Smuzhiyun				regulator-always-on;
287*4882a593Smuzhiyun				regulator-boot-on;
288*4882a593Smuzhiyun				regulator-state-mem {
289*4882a593Smuzhiyun					regulator-on-in-suspend;
290*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
291*4882a593Smuzhiyun				};
292*4882a593Smuzhiyun			};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun			vcc_ldo5: LDO_REG5 {
295*4882a593Smuzhiyun				regulator-name = "vcc_ldo5";
296*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
297*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
298*4882a593Smuzhiyun				regulator-boot-on;
299*4882a593Smuzhiyun				regulator-state-mem {
300*4882a593Smuzhiyun					regulator-off-in-suspend;
301*4882a593Smuzhiyun				};
302*4882a593Smuzhiyun			};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun			vcc_ldo6: LDO_REG6 {
305*4882a593Smuzhiyun				regulator-name = "vcc_ldo6";
306*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
307*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
308*4882a593Smuzhiyun				regulator-boot-on;
309*4882a593Smuzhiyun				regulator-state-mem {
310*4882a593Smuzhiyun					regulator-off-in-suspend;
311*4882a593Smuzhiyun				};
312*4882a593Smuzhiyun			};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun			vcc0v9_hdmi: LDO_REG7 {
315*4882a593Smuzhiyun				regulator-name = "vcc0v9_hdmi";
316*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
317*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
318*4882a593Smuzhiyun				regulator-always-on;
319*4882a593Smuzhiyun				regulator-boot-on;
320*4882a593Smuzhiyun				regulator-state-mem {
321*4882a593Smuzhiyun					regulator-off-in-suspend;
322*4882a593Smuzhiyun				};
323*4882a593Smuzhiyun			};
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun			vcc_efuse: LDO_REG8 {
326*4882a593Smuzhiyun				regulator-name = "vcc_efuse";
327*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
328*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
329*4882a593Smuzhiyun				regulator-always-on;
330*4882a593Smuzhiyun				regulator-boot-on;
331*4882a593Smuzhiyun				regulator-state-mem {
332*4882a593Smuzhiyun					regulator-off-in-suspend;
333*4882a593Smuzhiyun				};
334*4882a593Smuzhiyun			};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun			vcc3v3_s3: SWITCH_REG1 {
337*4882a593Smuzhiyun				regulator-name = "vcc3v3_s3";
338*4882a593Smuzhiyun				regulator-always-on;
339*4882a593Smuzhiyun				regulator-boot-on;
340*4882a593Smuzhiyun				regulator-state-mem {
341*4882a593Smuzhiyun					regulator-off-in-suspend;
342*4882a593Smuzhiyun				};
343*4882a593Smuzhiyun			};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun			vcc3v3_s0: SWITCH_REG2 {
346*4882a593Smuzhiyun				regulator-name = "vcc3v3_s0";
347*4882a593Smuzhiyun				regulator-always-on;
348*4882a593Smuzhiyun				regulator-boot-on;
349*4882a593Smuzhiyun				regulator-state-mem {
350*4882a593Smuzhiyun					regulator-off-in-suspend;
351*4882a593Smuzhiyun				};
352*4882a593Smuzhiyun			};
353*4882a593Smuzhiyun		};
354*4882a593Smuzhiyun	};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun	vdd_gpu: regulator@60 {
357*4882a593Smuzhiyun		compatible = "fcs,fan53555";
358*4882a593Smuzhiyun		reg = <0x60>;
359*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
360*4882a593Smuzhiyun		regulator-name = "vdd_gpu";
361*4882a593Smuzhiyun		regulator-min-microvolt = <600000>;
362*4882a593Smuzhiyun		regulator-max-microvolt = <1230000>;
363*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
364*4882a593Smuzhiyun		regulator-always-on;
365*4882a593Smuzhiyun		regulator-boot-on;
366*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
367*4882a593Smuzhiyun	};
368*4882a593Smuzhiyun};
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun&i2c7 {
371*4882a593Smuzhiyun	status = "okay";
372*4882a593Smuzhiyun	clock-frequency = <400000>;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun	fan: fan@18 {
375*4882a593Smuzhiyun		compatible = "ti,amc6821";
376*4882a593Smuzhiyun		reg = <0x18>;
377*4882a593Smuzhiyun		#cooling-cells = <2>;
378*4882a593Smuzhiyun	};
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun	rtc_twi: rtc@6f {
381*4882a593Smuzhiyun		compatible = "isil,isl1208";
382*4882a593Smuzhiyun		reg = <0x6f>;
383*4882a593Smuzhiyun	};
384*4882a593Smuzhiyun};
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun&i2c8 {
387*4882a593Smuzhiyun	status = "okay";
388*4882a593Smuzhiyun	clock-frequency = <400000>;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun	vdd_cpu_b: regulator@60 {
391*4882a593Smuzhiyun		compatible = "fcs,fan53555";
392*4882a593Smuzhiyun		reg = <0x60>;
393*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
394*4882a593Smuzhiyun		regulator-name = "vdd_cpu_b";
395*4882a593Smuzhiyun		regulator-min-microvolt = <600000>;
396*4882a593Smuzhiyun		regulator-max-microvolt = <1230000>;
397*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
398*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
399*4882a593Smuzhiyun		regulator-always-on;
400*4882a593Smuzhiyun		regulator-boot-on;
401*4882a593Smuzhiyun	};
402*4882a593Smuzhiyun};
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun&i2s0 {
405*4882a593Smuzhiyun	pinctrl-0 = <&i2s0_2ch_bus>;
406*4882a593Smuzhiyun	rockchip,playback-channels = <2>;
407*4882a593Smuzhiyun	rockchip,capture-channels = <2>;
408*4882a593Smuzhiyun	status = "okay";
409*4882a593Smuzhiyun};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun/*
412*4882a593Smuzhiyun * As Q7 does not specify neither a global nor a RX clock for I2S these
413*4882a593Smuzhiyun * signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO.
414*4882a593Smuzhiyun * Therefore we have to redefine the i2s0_2ch_bus definition to prevent
415*4882a593Smuzhiyun * conflicts.
416*4882a593Smuzhiyun */
417*4882a593Smuzhiyun&i2s0_2ch_bus {
418*4882a593Smuzhiyun	rockchip,pins =
419*4882a593Smuzhiyun		<3 RK_PD0 1 &pcfg_pull_none>,
420*4882a593Smuzhiyun		<3 RK_PD2 1 &pcfg_pull_none>,
421*4882a593Smuzhiyun		<3 RK_PD3 1 &pcfg_pull_none>,
422*4882a593Smuzhiyun		<3 RK_PD7 1 &pcfg_pull_none>;
423*4882a593Smuzhiyun};
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun&io_domains {
426*4882a593Smuzhiyun	status = "okay";
427*4882a593Smuzhiyun	bt656-supply = <&vcc_1v8>;
428*4882a593Smuzhiyun	audio-supply = <&vcc_1v8>;
429*4882a593Smuzhiyun	sdmmc-supply = <&vcc_sd>;
430*4882a593Smuzhiyun	gpio1830-supply = <&vcc_1v8>;
431*4882a593Smuzhiyun};
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun&pmu_io_domains {
434*4882a593Smuzhiyun	status = "okay";
435*4882a593Smuzhiyun	pmu1830-supply = <&vcc_1v8>;
436*4882a593Smuzhiyun};
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun&pwm2 {
439*4882a593Smuzhiyun	status = "okay";
440*4882a593Smuzhiyun};
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun&pinctrl {
443*4882a593Smuzhiyun	i2c8 {
444*4882a593Smuzhiyun		i2c8_xfer_a: i2c8-xfer {
445*4882a593Smuzhiyun			rockchip,pins =
446*4882a593Smuzhiyun			  <1 RK_PC4 1 &pcfg_pull_up>,
447*4882a593Smuzhiyun			  <1 RK_PC5 1 &pcfg_pull_up>;
448*4882a593Smuzhiyun		};
449*4882a593Smuzhiyun	};
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun	leds {
452*4882a593Smuzhiyun		module_led_pin: module-led-pin {
453*4882a593Smuzhiyun			rockchip,pins =
454*4882a593Smuzhiyun			  <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
455*4882a593Smuzhiyun		};
456*4882a593Smuzhiyun	};
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun	pmic {
459*4882a593Smuzhiyun		pmic_int_l: pmic-int-l {
460*4882a593Smuzhiyun			rockchip,pins =
461*4882a593Smuzhiyun			  <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
462*4882a593Smuzhiyun		};
463*4882a593Smuzhiyun	};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun	usb2 {
466*4882a593Smuzhiyun		vcc5v0_host_en: vcc5v0-host-en {
467*4882a593Smuzhiyun			rockchip,pins =
468*4882a593Smuzhiyun			  <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
469*4882a593Smuzhiyun		};
470*4882a593Smuzhiyun	};
471*4882a593Smuzhiyun};
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun&sdhci {
474*4882a593Smuzhiyun	/*
475*4882a593Smuzhiyun	 * Signal integrity isn't great at 200MHz but 100MHz has proven stable
476*4882a593Smuzhiyun	 * enough.
477*4882a593Smuzhiyun	 */
478*4882a593Smuzhiyun	max-frequency = <100000000>;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun	bus-width = <8>;
481*4882a593Smuzhiyun	mmc-hs400-1_8v;
482*4882a593Smuzhiyun	mmc-hs400-enhanced-strobe;
483*4882a593Smuzhiyun	non-removable;
484*4882a593Smuzhiyun	status = "okay";
485*4882a593Smuzhiyun};
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun&sdmmc {
488*4882a593Smuzhiyun	vqmmc-supply = <&vcc_sd>;
489*4882a593Smuzhiyun};
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun&spi1 {
492*4882a593Smuzhiyun	status = "okay";
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun	norflash: flash@0 {
495*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
496*4882a593Smuzhiyun		reg = <0>;
497*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
498*4882a593Smuzhiyun	};
499*4882a593Smuzhiyun};
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun&tcphy1 {
502*4882a593Smuzhiyun	status = "okay";
503*4882a593Smuzhiyun};
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun&tsadc {
506*4882a593Smuzhiyun	rockchip,hw-tshut-mode = <1>;
507*4882a593Smuzhiyun	rockchip,hw-tshut-polarity = <1>;
508*4882a593Smuzhiyun	status = "okay";
509*4882a593Smuzhiyun};
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun&u2phy1 {
512*4882a593Smuzhiyun	status = "okay";
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun	u2phy1_otg: otg-port {
515*4882a593Smuzhiyun		status = "okay";
516*4882a593Smuzhiyun	};
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun	u2phy1_host: host-port {
519*4882a593Smuzhiyun		phy-supply = <&vcc5v0_host>;
520*4882a593Smuzhiyun		status = "okay";
521*4882a593Smuzhiyun	};
522*4882a593Smuzhiyun};
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun&usbdrd3_1 {
525*4882a593Smuzhiyun	status = "okay";
526*4882a593Smuzhiyun};
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun&usbdrd_dwc3_1 {
529*4882a593Smuzhiyun	status = "okay";
530*4882a593Smuzhiyun	dr_mode = "host";
531*4882a593Smuzhiyun};
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun&usb_host1_ehci {
534*4882a593Smuzhiyun	status = "okay";
535*4882a593Smuzhiyun};
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun&usb_host1_ohci {
538*4882a593Smuzhiyun	status = "okay";
539*4882a593Smuzhiyun};
540