1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "dra71x.dtsi" 7*4882a593Smuzhiyun#include "dra7-mmc-iodelay.dtsi" 8*4882a593Smuzhiyun#include "dra72x-mmc-iodelay.dtsi" 9*4882a593Smuzhiyun#include <dt-bindings/net/ti-dp83867.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"; 13*4882a593Smuzhiyun model = "TI DRA718 EVM"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun memory { 16*4882a593Smuzhiyun device_type = "memory"; 17*4882a593Smuzhiyun reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reserved-memory { 21*4882a593Smuzhiyun #address-cells = <2>; 22*4882a593Smuzhiyun #size-cells = <2>; 23*4882a593Smuzhiyun ranges; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun ipu2_memory_region: ipu2-memory@95800000 { 26*4882a593Smuzhiyun compatible = "shared-dma-pool"; 27*4882a593Smuzhiyun reg = <0x0 0x95800000 0x0 0x3800000>; 28*4882a593Smuzhiyun reusable; 29*4882a593Smuzhiyun status = "okay"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun dsp1_memory_region: dsp1-memory@99000000 { 33*4882a593Smuzhiyun compatible = "shared-dma-pool"; 34*4882a593Smuzhiyun reg = <0x0 0x99000000 0x0 0x4000000>; 35*4882a593Smuzhiyun reusable; 36*4882a593Smuzhiyun status = "okay"; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun ipu1_memory_region: ipu1-memory@9d000000 { 40*4882a593Smuzhiyun compatible = "shared-dma-pool"; 41*4882a593Smuzhiyun reg = <0x0 0x9d000000 0x0 0x2000000>; 42*4882a593Smuzhiyun reusable; 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun vpo_sd_1v8_3v3: gpio-regulator-TPS74801 { 48*4882a593Smuzhiyun compatible = "regulator-gpio"; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun regulator-name = "vddshv8"; 51*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 52*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 53*4882a593Smuzhiyun regulator-boot-on; 54*4882a593Smuzhiyun vin-supply = <&evm_5v0>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; 57*4882a593Smuzhiyun states = <1800000 0x0 58*4882a593Smuzhiyun 3300000 0x1>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun evm_1v8_sw: fixedregulator-evm_1v8 { 62*4882a593Smuzhiyun compatible = "regulator-fixed"; 63*4882a593Smuzhiyun regulator-name = "evm_1v8"; 64*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 65*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 66*4882a593Smuzhiyun vin-supply = <&lp8732_buck0_reg>; 67*4882a593Smuzhiyun regulator-always-on; 68*4882a593Smuzhiyun regulator-boot-on; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun poweroff: gpio-poweroff { 72*4882a593Smuzhiyun compatible = "gpio-poweroff"; 73*4882a593Smuzhiyun gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>; 74*4882a593Smuzhiyun input; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun&i2c1 { 79*4882a593Smuzhiyun status = "okay"; 80*4882a593Smuzhiyun clock-frequency = <400000>; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun lp8733: lp8733@60 { 83*4882a593Smuzhiyun compatible = "ti,lp8733"; 84*4882a593Smuzhiyun reg = <0x60>; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun buck0-in-supply =<&vsys_3v3>; 87*4882a593Smuzhiyun buck1-in-supply =<&vsys_3v3>; 88*4882a593Smuzhiyun ldo0-in-supply =<&evm_5v0>; 89*4882a593Smuzhiyun ldo1-in-supply =<&evm_5v0>; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun lp8733_regulators: regulators { 92*4882a593Smuzhiyun lp8733_buck0_reg: buck0 { 93*4882a593Smuzhiyun /* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */ 94*4882a593Smuzhiyun regulator-name = "lp8733-buck0"; 95*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 96*4882a593Smuzhiyun regulator-max-microvolt = <1250000>; 97*4882a593Smuzhiyun regulator-always-on; 98*4882a593Smuzhiyun regulator-boot-on; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun lp8733_buck1_reg: buck1 { 102*4882a593Smuzhiyun /* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */ 103*4882a593Smuzhiyun regulator-name = "lp8733-buck1"; 104*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 105*4882a593Smuzhiyun regulator-max-microvolt = <1250000>; 106*4882a593Smuzhiyun regulator-boot-on; 107*4882a593Smuzhiyun regulator-always-on; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun lp8733_ldo0_reg: ldo0 { 111*4882a593Smuzhiyun /* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */ 112*4882a593Smuzhiyun regulator-name = "lp8733-ldo0"; 113*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 114*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun lp8733_ldo1_reg: ldo1 { 118*4882a593Smuzhiyun /* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */ 119*4882a593Smuzhiyun regulator-name = "lp8733-ldo1"; 120*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 121*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 122*4882a593Smuzhiyun regulator-always-on; 123*4882a593Smuzhiyun regulator-boot-on; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun lp8732: lp8732@61 { 129*4882a593Smuzhiyun compatible = "ti,lp8732"; 130*4882a593Smuzhiyun reg = <0x61>; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun buck0-in-supply =<&vsys_3v3>; 133*4882a593Smuzhiyun buck1-in-supply =<&vsys_3v3>; 134*4882a593Smuzhiyun ldo0-in-supply =<&vsys_3v3>; 135*4882a593Smuzhiyun ldo1-in-supply =<&vsys_3v3>; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun lp8732_regulators: regulators { 138*4882a593Smuzhiyun lp8732_buck0_reg: buck0 { 139*4882a593Smuzhiyun /* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */ 140*4882a593Smuzhiyun regulator-name = "lp8732-buck0"; 141*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 142*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 143*4882a593Smuzhiyun regulator-always-on; 144*4882a593Smuzhiyun regulator-boot-on; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun lp8732_buck1_reg: buck1 { 148*4882a593Smuzhiyun /* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */ 149*4882a593Smuzhiyun regulator-name = "lp8732-buck1"; 150*4882a593Smuzhiyun regulator-min-microvolt = <1350000>; 151*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 152*4882a593Smuzhiyun regulator-boot-on; 153*4882a593Smuzhiyun regulator-always-on; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun lp8732_ldo0_reg: ldo0 { 157*4882a593Smuzhiyun /* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */ 158*4882a593Smuzhiyun regulator-name = "lp8732-ldo0"; 159*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 160*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 161*4882a593Smuzhiyun regulator-boot-on; 162*4882a593Smuzhiyun regulator-always-on; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun lp8732_ldo1_reg: ldo1 { 166*4882a593Smuzhiyun /* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */ 167*4882a593Smuzhiyun regulator-name = "lp8732-ldo1"; 168*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 169*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 170*4882a593Smuzhiyun regulator-always-on; 171*4882a593Smuzhiyun regulator-boot-on; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun}; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun&pcf_lcd { 178*4882a593Smuzhiyun interrupt-parent = <&gpio7>; 179*4882a593Smuzhiyun interrupts = <31 IRQ_TYPE_EDGE_FALLING>; 180*4882a593Smuzhiyun}; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun&pcf_gpio_21 { 183*4882a593Smuzhiyun interrupt-parent = <&gpio7>; 184*4882a593Smuzhiyun interrupts = <31 IRQ_TYPE_EDGE_FALLING>; 185*4882a593Smuzhiyun}; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun&pcf_hdmi { 188*4882a593Smuzhiyun p0 { 189*4882a593Smuzhiyun /* 190*4882a593Smuzhiyun * PM_OEn to High: Disable routing I2C3 to PM_I2C 191*4882a593Smuzhiyun * With this PM_SEL(p3) should not matter 192*4882a593Smuzhiyun */ 193*4882a593Smuzhiyun gpio-hog; 194*4882a593Smuzhiyun gpios = <0 GPIO_ACTIVE_LOW>; 195*4882a593Smuzhiyun output-high; 196*4882a593Smuzhiyun line-name = "pm_oe_n"; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun}; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun&mmc1 { 201*4882a593Smuzhiyun pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; 202*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; 203*4882a593Smuzhiyun pinctrl-1 = <&mmc1_pins_hs>; 204*4882a593Smuzhiyun pinctrl-2 = <&mmc1_pins_sdr12>; 205*4882a593Smuzhiyun pinctrl-3 = <&mmc1_pins_sdr25>; 206*4882a593Smuzhiyun pinctrl-4 = <&mmc1_pins_sdr50>; 207*4882a593Smuzhiyun pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; 208*4882a593Smuzhiyun pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; 209*4882a593Smuzhiyun vqmmc-supply = <&vpo_sd_1v8_3v3>; 210*4882a593Smuzhiyun}; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun&mmc2 { 213*4882a593Smuzhiyun pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; 214*4882a593Smuzhiyun pinctrl-0 = <&mmc2_pins_default>; 215*4882a593Smuzhiyun pinctrl-1 = <&mmc2_pins_hs>; 216*4882a593Smuzhiyun pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; 217*4882a593Smuzhiyun pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; 218*4882a593Smuzhiyun vmmc-supply = <&evm_1v8_sw>; 219*4882a593Smuzhiyun vqmmc-supply = <&evm_1v8_sw>; 220*4882a593Smuzhiyun}; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun&mac_sw { 223*4882a593Smuzhiyun mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, 224*4882a593Smuzhiyun <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ 225*4882a593Smuzhiyun <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ 226*4882a593Smuzhiyun status = "okay"; 227*4882a593Smuzhiyun}; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun&cpsw_port1 { 230*4882a593Smuzhiyun phy-handle = <&dp83867_0>; 231*4882a593Smuzhiyun phy-mode = "rgmii-id"; 232*4882a593Smuzhiyun ti,dual-emac-pvid = <1>; 233*4882a593Smuzhiyun}; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun&cpsw_port2 { 236*4882a593Smuzhiyun phy-handle = <&dp83867_1>; 237*4882a593Smuzhiyun phy-mode = "rgmii-id"; 238*4882a593Smuzhiyun ti,dual-emac-pvid = <2>; 239*4882a593Smuzhiyun}; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun&davinci_mdio_sw { 242*4882a593Smuzhiyun dp83867_0: ethernet-phy@2 { 243*4882a593Smuzhiyun reg = <2>; 244*4882a593Smuzhiyun ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 245*4882a593Smuzhiyun ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; 246*4882a593Smuzhiyun ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; 247*4882a593Smuzhiyun ti,min-output-impedance; 248*4882a593Smuzhiyun ti,dp83867-rxctrl-strap-quirk; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun dp83867_1: ethernet-phy@3 { 252*4882a593Smuzhiyun reg = <3>; 253*4882a593Smuzhiyun ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 254*4882a593Smuzhiyun ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; 255*4882a593Smuzhiyun ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; 256*4882a593Smuzhiyun ti,min-output-impedance; 257*4882a593Smuzhiyun ti,dp83867-rxctrl-strap-quirk; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun}; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun/* No Sata on this device */ 262*4882a593Smuzhiyun&sata_phy { 263*4882a593Smuzhiyun status = "disabled"; 264*4882a593Smuzhiyun}; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun&sata { 267*4882a593Smuzhiyun status = "disabled"; 268*4882a593Smuzhiyun}; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun/* No RTC on this device */ 271*4882a593Smuzhiyun&rtc { 272*4882a593Smuzhiyun status = "disabled"; 273*4882a593Smuzhiyun}; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun&usb2_phy1 { 276*4882a593Smuzhiyun phy-supply = <&lp8733_ldo1_reg>; 277*4882a593Smuzhiyun}; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun&usb2_phy2 { 280*4882a593Smuzhiyun phy-supply = <&lp8733_ldo1_reg>; 281*4882a593Smuzhiyun}; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun&dss { 284*4882a593Smuzhiyun /* Supplied by VDA_1V8_PLL */ 285*4882a593Smuzhiyun vdda_video-supply = <&lp8732_ldo0_reg>; 286*4882a593Smuzhiyun}; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun&hdmi { 289*4882a593Smuzhiyun /* Supplied by VDA_1V8_PHY */ 290*4882a593Smuzhiyun vdda_video-supply = <&lp8732_ldo1_reg>; 291*4882a593Smuzhiyun}; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun&extcon_usb1 { 294*4882a593Smuzhiyun vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; 295*4882a593Smuzhiyun}; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun&extcon_usb2 { 298*4882a593Smuzhiyun vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; 299*4882a593Smuzhiyun}; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun&ipu2 { 302*4882a593Smuzhiyun status = "okay"; 303*4882a593Smuzhiyun memory-region = <&ipu2_memory_region>; 304*4882a593Smuzhiyun}; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun&ipu1 { 307*4882a593Smuzhiyun status = "okay"; 308*4882a593Smuzhiyun memory-region = <&ipu1_memory_region>; 309*4882a593Smuzhiyun}; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun&dsp1 { 312*4882a593Smuzhiyun status = "okay"; 313*4882a593Smuzhiyun memory-region = <&dsp1_memory_region>; 314*4882a593Smuzhiyun}; 315