1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "dra76x.dtsi" 8*4882a593Smuzhiyun#include "dra7-evm-common.dtsi" 9*4882a593Smuzhiyun#include "dra76x-mmc-iodelay.dtsi" 10*4882a593Smuzhiyun#include <dt-bindings/net/ti-dp83867.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "TI DRA762 EVM"; 14*4882a593Smuzhiyun compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun aliases { 17*4882a593Smuzhiyun display0 = &hdmi0; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun sound0 = &sound0; 20*4882a593Smuzhiyun sound1 = &hdmi; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun memory@0 { 24*4882a593Smuzhiyun device_type = "memory"; 25*4882a593Smuzhiyun reg = <0x0 0x80000000 0x0 0x80000000>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun reserved-memory { 29*4882a593Smuzhiyun #address-cells = <2>; 30*4882a593Smuzhiyun #size-cells = <2>; 31*4882a593Smuzhiyun ranges; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun ipu2_cma_pool: ipu2_cma@95800000 { 34*4882a593Smuzhiyun compatible = "shared-dma-pool"; 35*4882a593Smuzhiyun reg = <0x0 0x95800000 0x0 0x3800000>; 36*4882a593Smuzhiyun reusable; 37*4882a593Smuzhiyun status = "okay"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun dsp1_cma_pool: dsp1_cma@99000000 { 41*4882a593Smuzhiyun compatible = "shared-dma-pool"; 42*4882a593Smuzhiyun reg = <0x0 0x99000000 0x0 0x4000000>; 43*4882a593Smuzhiyun reusable; 44*4882a593Smuzhiyun status = "okay"; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun ipu1_cma_pool: ipu1_cma@9d000000 { 48*4882a593Smuzhiyun compatible = "shared-dma-pool"; 49*4882a593Smuzhiyun reg = <0x0 0x9d000000 0x0 0x2000000>; 50*4882a593Smuzhiyun reusable; 51*4882a593Smuzhiyun status = "okay"; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun dsp2_cma_pool: dsp2_cma@9f000000 { 55*4882a593Smuzhiyun compatible = "shared-dma-pool"; 56*4882a593Smuzhiyun reg = <0x0 0x9f000000 0x0 0x800000>; 57*4882a593Smuzhiyun reusable; 58*4882a593Smuzhiyun status = "okay"; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun vsys_12v0: fixedregulator-vsys12v0 { 63*4882a593Smuzhiyun /* main supply */ 64*4882a593Smuzhiyun compatible = "regulator-fixed"; 65*4882a593Smuzhiyun regulator-name = "vsys_12v0"; 66*4882a593Smuzhiyun regulator-min-microvolt = <12000000>; 67*4882a593Smuzhiyun regulator-max-microvolt = <12000000>; 68*4882a593Smuzhiyun regulator-always-on; 69*4882a593Smuzhiyun regulator-boot-on; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun vsys_5v0: fixedregulator-vsys5v0 { 73*4882a593Smuzhiyun /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */ 74*4882a593Smuzhiyun compatible = "regulator-fixed"; 75*4882a593Smuzhiyun regulator-name = "vsys_5v0"; 76*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 77*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 78*4882a593Smuzhiyun vin-supply = <&vsys_12v0>; 79*4882a593Smuzhiyun regulator-always-on; 80*4882a593Smuzhiyun regulator-boot-on; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun vio_3v6: fixedregulator-vio_3v6 { 84*4882a593Smuzhiyun compatible = "regulator-fixed"; 85*4882a593Smuzhiyun regulator-name = "vio_3v6"; 86*4882a593Smuzhiyun regulator-min-microvolt = <3600000>; 87*4882a593Smuzhiyun regulator-max-microvolt = <3600000>; 88*4882a593Smuzhiyun vin-supply = <&vsys_5v0>; 89*4882a593Smuzhiyun regulator-always-on; 90*4882a593Smuzhiyun regulator-boot-on; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun vsys_3v3: fixedregulator-vsys3v3 { 94*4882a593Smuzhiyun /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */ 95*4882a593Smuzhiyun compatible = "regulator-fixed"; 96*4882a593Smuzhiyun regulator-name = "vsys_3v3"; 97*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 98*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 99*4882a593Smuzhiyun vin-supply = <&vsys_12v0>; 100*4882a593Smuzhiyun regulator-always-on; 101*4882a593Smuzhiyun regulator-boot-on; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun vio_3v3: fixedregulator-vio_3v3 { 105*4882a593Smuzhiyun compatible = "regulator-fixed"; 106*4882a593Smuzhiyun regulator-name = "vio_3v3"; 107*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 108*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 109*4882a593Smuzhiyun vin-supply = <&vsys_3v3>; 110*4882a593Smuzhiyun regulator-always-on; 111*4882a593Smuzhiyun regulator-boot-on; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun vio_3v3_sd: fixedregulator-sd { 115*4882a593Smuzhiyun compatible = "regulator-fixed"; 116*4882a593Smuzhiyun regulator-name = "vio_3v3_sd"; 117*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 118*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 119*4882a593Smuzhiyun vin-supply = <&vio_3v3>; 120*4882a593Smuzhiyun enable-active-high; 121*4882a593Smuzhiyun gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun vio_1v8: fixedregulator-vio_1v8 { 125*4882a593Smuzhiyun compatible = "regulator-fixed"; 126*4882a593Smuzhiyun regulator-name = "vio_1v8"; 127*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 128*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 129*4882a593Smuzhiyun vin-supply = <&smps5_reg>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun vmmcwl_fixed: fixedregulator-mmcwl { 133*4882a593Smuzhiyun compatible = "regulator-fixed"; 134*4882a593Smuzhiyun regulator-name = "vmmcwl_fixed"; 135*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 136*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 137*4882a593Smuzhiyun gpio = <&gpio5 8 0>; /* gpio5_8 */ 138*4882a593Smuzhiyun startup-delay-us = <70000>; 139*4882a593Smuzhiyun enable-active-high; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun vtt_fixed: fixedregulator-vtt { 143*4882a593Smuzhiyun compatible = "regulator-fixed"; 144*4882a593Smuzhiyun regulator-name = "vtt_fixed"; 145*4882a593Smuzhiyun regulator-min-microvolt = <1350000>; 146*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 147*4882a593Smuzhiyun vin-supply = <&vsys_3v3>; 148*4882a593Smuzhiyun regulator-always-on; 149*4882a593Smuzhiyun regulator-boot-on; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun aic_dvdd: fixedregulator-aic_dvdd { 153*4882a593Smuzhiyun /* TPS77018DBVT */ 154*4882a593Smuzhiyun compatible = "regulator-fixed"; 155*4882a593Smuzhiyun regulator-name = "aic_dvdd"; 156*4882a593Smuzhiyun vin-supply = <&vio_3v3>; 157*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 158*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun clk_ov5640_fixed: clock { 162*4882a593Smuzhiyun compatible = "fixed-clock"; 163*4882a593Smuzhiyun #clock-cells = <0>; 164*4882a593Smuzhiyun clock-frequency = <24000000>; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun hdmi0: connector { 168*4882a593Smuzhiyun compatible = "hdmi-connector"; 169*4882a593Smuzhiyun label = "hdmi"; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun type = "a"; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun port { 174*4882a593Smuzhiyun hdmi_connector_in: endpoint { 175*4882a593Smuzhiyun remote-endpoint = <&tpd12s015_out>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun tpd12s015: encoder { 181*4882a593Smuzhiyun compatible = "ti,tpd12s015"; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */ 184*4882a593Smuzhiyun <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */ 185*4882a593Smuzhiyun <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun ports { 188*4882a593Smuzhiyun #address-cells = <1>; 189*4882a593Smuzhiyun #size-cells = <0>; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun port@0 { 192*4882a593Smuzhiyun reg = <0>; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun tpd12s015_in: endpoint { 195*4882a593Smuzhiyun remote-endpoint = <&hdmi_out>; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun port@1 { 200*4882a593Smuzhiyun reg = <1>; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun tpd12s015_out: endpoint { 203*4882a593Smuzhiyun remote-endpoint = <&hdmi_connector_in>; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun}; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun&i2c1 { 211*4882a593Smuzhiyun status = "okay"; 212*4882a593Smuzhiyun clock-frequency = <400000>; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun tps65917: tps65917@58 { 215*4882a593Smuzhiyun compatible = "ti,tps65917"; 216*4882a593Smuzhiyun reg = <0x58>; 217*4882a593Smuzhiyun ti,system-power-controller; 218*4882a593Smuzhiyun ti,palmas-override-powerhold; 219*4882a593Smuzhiyun interrupt-controller; 220*4882a593Smuzhiyun #interrupt-cells = <2>; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun tps65917_pmic { 223*4882a593Smuzhiyun compatible = "ti,tps65917-pmic"; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun smps12-in-supply = <&vsys_3v3>; 226*4882a593Smuzhiyun smps3-in-supply = <&vsys_3v3>; 227*4882a593Smuzhiyun smps4-in-supply = <&vsys_3v3>; 228*4882a593Smuzhiyun smps5-in-supply = <&vsys_3v3>; 229*4882a593Smuzhiyun ldo1-in-supply = <&vsys_3v3>; 230*4882a593Smuzhiyun ldo2-in-supply = <&vsys_3v3>; 231*4882a593Smuzhiyun ldo3-in-supply = <&vsys_5v0>; 232*4882a593Smuzhiyun ldo4-in-supply = <&vsys_5v0>; 233*4882a593Smuzhiyun ldo5-in-supply = <&vsys_3v3>; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun tps65917_regulators: regulators { 236*4882a593Smuzhiyun smps12_reg: smps12 { 237*4882a593Smuzhiyun /* VDD_DSPEVE */ 238*4882a593Smuzhiyun regulator-name = "smps12"; 239*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 240*4882a593Smuzhiyun regulator-max-microvolt = <1250000>; 241*4882a593Smuzhiyun regulator-always-on; 242*4882a593Smuzhiyun regulator-boot-on; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun smps3_reg: smps3 { 246*4882a593Smuzhiyun /* VDD_CORE */ 247*4882a593Smuzhiyun regulator-name = "smps3"; 248*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 249*4882a593Smuzhiyun regulator-max-microvolt = <1250000>; 250*4882a593Smuzhiyun regulator-boot-on; 251*4882a593Smuzhiyun regulator-always-on; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun smps4_reg: smps4 { 255*4882a593Smuzhiyun /* VDD_IVA */ 256*4882a593Smuzhiyun regulator-name = "smps4"; 257*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 258*4882a593Smuzhiyun regulator-max-microvolt = <1250000>; 259*4882a593Smuzhiyun regulator-always-on; 260*4882a593Smuzhiyun regulator-boot-on; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun smps5_reg: smps5 { 264*4882a593Smuzhiyun /* VDDS1V8 */ 265*4882a593Smuzhiyun regulator-name = "smps5"; 266*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 267*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 268*4882a593Smuzhiyun regulator-boot-on; 269*4882a593Smuzhiyun regulator-always-on; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun ldo1_reg: ldo1 { 273*4882a593Smuzhiyun /* LDO1_OUT --> VDA_PHY1_1V8 */ 274*4882a593Smuzhiyun regulator-name = "ldo1"; 275*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 276*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 277*4882a593Smuzhiyun regulator-always-on; 278*4882a593Smuzhiyun regulator-boot-on; 279*4882a593Smuzhiyun regulator-allow-bypass; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun ldo2_reg: ldo2 { 283*4882a593Smuzhiyun /* LDO2_OUT --> VDA_PHY2_1V8 */ 284*4882a593Smuzhiyun regulator-name = "ldo2"; 285*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 286*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 287*4882a593Smuzhiyun regulator-allow-bypass; 288*4882a593Smuzhiyun regulator-always-on; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun ldo3_reg: ldo3 { 292*4882a593Smuzhiyun /* VDA_USB_3V3 */ 293*4882a593Smuzhiyun regulator-name = "ldo3"; 294*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 295*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 296*4882a593Smuzhiyun regulator-boot-on; 297*4882a593Smuzhiyun regulator-always-on; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun ldo5_reg: ldo5 { 301*4882a593Smuzhiyun /* VDDA_1V8_PLL */ 302*4882a593Smuzhiyun regulator-name = "ldo5"; 303*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 304*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 305*4882a593Smuzhiyun regulator-always-on; 306*4882a593Smuzhiyun regulator-boot-on; 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun ldo4_reg: ldo4 { 310*4882a593Smuzhiyun /* VDD_SDIO_DV */ 311*4882a593Smuzhiyun regulator-name = "ldo4"; 312*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 313*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 314*4882a593Smuzhiyun regulator-boot-on; 315*4882a593Smuzhiyun regulator-always-on; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun tps65917_power_button { 321*4882a593Smuzhiyun compatible = "ti,palmas-pwrbutton"; 322*4882a593Smuzhiyun interrupt-parent = <&tps65917>; 323*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_NONE>; 324*4882a593Smuzhiyun wakeup-source; 325*4882a593Smuzhiyun ti,palmas-long-press-seconds = <6>; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun lp87565: lp87565@60 { 330*4882a593Smuzhiyun compatible = "ti,lp87565-q1"; 331*4882a593Smuzhiyun reg = <0x60>; 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun buck10-in-supply =<&vsys_3v3>; 334*4882a593Smuzhiyun buck23-in-supply =<&vsys_3v3>; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun regulators: regulators { 337*4882a593Smuzhiyun buck10_reg: buck10 { 338*4882a593Smuzhiyun /*VDD_MPU*/ 339*4882a593Smuzhiyun regulator-name = "buck10"; 340*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 341*4882a593Smuzhiyun regulator-max-microvolt = <1250000>; 342*4882a593Smuzhiyun regulator-always-on; 343*4882a593Smuzhiyun regulator-boot-on; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun buck23_reg: buck23 { 347*4882a593Smuzhiyun /* VDD_GPU*/ 348*4882a593Smuzhiyun regulator-name = "buck23"; 349*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 350*4882a593Smuzhiyun regulator-max-microvolt = <1250000>; 351*4882a593Smuzhiyun regulator-boot-on; 352*4882a593Smuzhiyun regulator-always-on; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun }; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun pcf_lcd: pcf8757@20 { 358*4882a593Smuzhiyun compatible = "ti,pcf8575", "nxp,pcf8575"; 359*4882a593Smuzhiyun reg = <0x20>; 360*4882a593Smuzhiyun gpio-controller; 361*4882a593Smuzhiyun #gpio-cells = <2>; 362*4882a593Smuzhiyun interrupt-controller; 363*4882a593Smuzhiyun #interrupt-cells = <2>; 364*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 365*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun pcf_gpio_21: pcf8757@21 { 369*4882a593Smuzhiyun compatible = "ti,pcf8575", "nxp,pcf8575"; 370*4882a593Smuzhiyun reg = <0x21>; 371*4882a593Smuzhiyun gpio-controller; 372*4882a593Smuzhiyun #gpio-cells = <2>; 373*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 374*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 375*4882a593Smuzhiyun interrupt-controller; 376*4882a593Smuzhiyun #interrupt-cells = <2>; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun pcf_hdmi: pcf8575@26 { 380*4882a593Smuzhiyun compatible = "ti,pcf8575", "nxp,pcf8575"; 381*4882a593Smuzhiyun reg = <0x26>; 382*4882a593Smuzhiyun gpio-controller; 383*4882a593Smuzhiyun #gpio-cells = <2>; 384*4882a593Smuzhiyun p1 { 385*4882a593Smuzhiyun /* vin6_sel_s0: high: VIN6, low: audio */ 386*4882a593Smuzhiyun gpio-hog; 387*4882a593Smuzhiyun gpios = <1 GPIO_ACTIVE_HIGH>; 388*4882a593Smuzhiyun output-low; 389*4882a593Smuzhiyun line-name = "vin6_sel_s0"; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun tlv320aic3106: tlv320aic3106@19 { 394*4882a593Smuzhiyun #sound-dai-cells = <0>; 395*4882a593Smuzhiyun compatible = "ti,tlv320aic3106"; 396*4882a593Smuzhiyun reg = <0x19>; 397*4882a593Smuzhiyun adc-settle-ms = <40>; 398*4882a593Smuzhiyun ai3x-micbias-vg = <1>; /* 2.0V */ 399*4882a593Smuzhiyun status = "okay"; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun /* Regulators */ 402*4882a593Smuzhiyun AVDD-supply = <&vio_3v3>; 403*4882a593Smuzhiyun IOVDD-supply = <&vio_3v3>; 404*4882a593Smuzhiyun DRVDD-supply = <&vio_3v3>; 405*4882a593Smuzhiyun DVDD-supply = <&aic_dvdd>; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun}; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun&i2c5 { 410*4882a593Smuzhiyun status = "okay"; 411*4882a593Smuzhiyun clock-frequency = <400000>; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun ov5640@3c { 414*4882a593Smuzhiyun compatible = "ovti,ov5640"; 415*4882a593Smuzhiyun reg = <0x3c>; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun clocks = <&clk_ov5640_fixed>; 418*4882a593Smuzhiyun clock-names = "xclk"; 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun port { 421*4882a593Smuzhiyun csi2_cam0: endpoint { 422*4882a593Smuzhiyun remote-endpoint = <&csi2_phy0>; 423*4882a593Smuzhiyun clock-lanes = <0>; 424*4882a593Smuzhiyun data-lanes = <1 2>; 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun }; 428*4882a593Smuzhiyun}; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun&cpu0 { 431*4882a593Smuzhiyun vdd-supply = <&buck10_reg>; 432*4882a593Smuzhiyun}; 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun&mmc1 { 435*4882a593Smuzhiyun status = "okay"; 436*4882a593Smuzhiyun vmmc-supply = <&vio_3v3_sd>; 437*4882a593Smuzhiyun vqmmc-supply = <&ldo4_reg>; 438*4882a593Smuzhiyun bus-width = <4>; 439*4882a593Smuzhiyun /* 440*4882a593Smuzhiyun * SDCD signal is not being used here - using the fact that GPIO mode 441*4882a593Smuzhiyun * is always hardwired. 442*4882a593Smuzhiyun */ 443*4882a593Smuzhiyun cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; 444*4882a593Smuzhiyun pinctrl-names = "default", "hs"; 445*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins_default>; 446*4882a593Smuzhiyun pinctrl-1 = <&mmc1_pins_hs>; 447*4882a593Smuzhiyun}; 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun&mmc2 { 450*4882a593Smuzhiyun status = "okay"; 451*4882a593Smuzhiyun vmmc-supply = <&vio_1v8>; 452*4882a593Smuzhiyun vqmmc-supply = <&vio_1v8>; 453*4882a593Smuzhiyun bus-width = <8>; 454*4882a593Smuzhiyun non-removable; 455*4882a593Smuzhiyun pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; 456*4882a593Smuzhiyun pinctrl-0 = <&mmc2_pins_default>; 457*4882a593Smuzhiyun pinctrl-1 = <&mmc2_pins_default>; 458*4882a593Smuzhiyun pinctrl-2 = <&mmc2_pins_default>; 459*4882a593Smuzhiyun pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>; 460*4882a593Smuzhiyun}; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun&mmc4 { 463*4882a593Smuzhiyun status = "okay"; 464*4882a593Smuzhiyun vmmc-supply = <&vio_3v6>; 465*4882a593Smuzhiyun vqmmc-supply = <&vmmcwl_fixed>; 466*4882a593Smuzhiyun pinctrl-names = "default", "hs", "sdr12", "sdr25"; 467*4882a593Smuzhiyun pinctrl-0 = <&mmc4_pins_hs &mmc4_iodelay_default_conf>; 468*4882a593Smuzhiyun pinctrl-1 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; 469*4882a593Smuzhiyun pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; 470*4882a593Smuzhiyun pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; 471*4882a593Smuzhiyun}; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun/* No RTC on this device */ 474*4882a593Smuzhiyun&rtc { 475*4882a593Smuzhiyun status = "disabled"; 476*4882a593Smuzhiyun}; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun&mac_sw { 479*4882a593Smuzhiyun status = "okay"; 480*4882a593Smuzhiyun}; 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun&cpsw_port1 { 483*4882a593Smuzhiyun phy-handle = <&dp83867_0>; 484*4882a593Smuzhiyun phy-mode = "rgmii-id"; 485*4882a593Smuzhiyun ti,dual-emac-pvid = <1>; 486*4882a593Smuzhiyun}; 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun&cpsw_port2 { 489*4882a593Smuzhiyun phy-handle = <&dp83867_1>; 490*4882a593Smuzhiyun phy-mode = "rgmii-id"; 491*4882a593Smuzhiyun ti,dual-emac-pvid = <2>; 492*4882a593Smuzhiyun}; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun&davinci_mdio_sw { 495*4882a593Smuzhiyun dp83867_0: ethernet-phy@2 { 496*4882a593Smuzhiyun reg = <2>; 497*4882a593Smuzhiyun ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 498*4882a593Smuzhiyun ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; 499*4882a593Smuzhiyun ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; 500*4882a593Smuzhiyun ti,min-output-impedance; 501*4882a593Smuzhiyun ti,dp83867-rxctrl-strap-quirk; 502*4882a593Smuzhiyun }; 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun dp83867_1: ethernet-phy@3 { 505*4882a593Smuzhiyun reg = <3>; 506*4882a593Smuzhiyun ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 507*4882a593Smuzhiyun ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; 508*4882a593Smuzhiyun ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; 509*4882a593Smuzhiyun ti,min-output-impedance; 510*4882a593Smuzhiyun ti,dp83867-rxctrl-strap-quirk; 511*4882a593Smuzhiyun }; 512*4882a593Smuzhiyun}; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun&usb2_phy1 { 515*4882a593Smuzhiyun phy-supply = <&ldo3_reg>; 516*4882a593Smuzhiyun}; 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun&usb2_phy2 { 519*4882a593Smuzhiyun phy-supply = <&ldo3_reg>; 520*4882a593Smuzhiyun}; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun&dss { 523*4882a593Smuzhiyun status = "okay"; 524*4882a593Smuzhiyun vdda_video-supply = <&ldo5_reg>; 525*4882a593Smuzhiyun}; 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun&hdmi { 528*4882a593Smuzhiyun status = "okay"; 529*4882a593Smuzhiyun 530*4882a593Smuzhiyun vdda-supply = <&ldo1_reg>; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun port { 533*4882a593Smuzhiyun hdmi_out: endpoint { 534*4882a593Smuzhiyun remote-endpoint = <&tpd12s015_in>; 535*4882a593Smuzhiyun }; 536*4882a593Smuzhiyun }; 537*4882a593Smuzhiyun}; 538*4882a593Smuzhiyun 539*4882a593Smuzhiyun&qspi { 540*4882a593Smuzhiyun spi-max-frequency = <96000000>; 541*4882a593Smuzhiyun m25p80@0 { 542*4882a593Smuzhiyun spi-max-frequency = <96000000>; 543*4882a593Smuzhiyun }; 544*4882a593Smuzhiyun}; 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun&pcie2_phy { 547*4882a593Smuzhiyun status = "okay"; 548*4882a593Smuzhiyun}; 549*4882a593Smuzhiyun 550*4882a593Smuzhiyun&pcie1_rc { 551*4882a593Smuzhiyun num-lanes = <2>; 552*4882a593Smuzhiyun phys = <&pcie1_phy>, <&pcie2_phy>; 553*4882a593Smuzhiyun phy-names = "pcie-phy0", "pcie-phy1"; 554*4882a593Smuzhiyun}; 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun&pcie1_ep { 557*4882a593Smuzhiyun num-lanes = <2>; 558*4882a593Smuzhiyun phys = <&pcie1_phy>, <&pcie2_phy>; 559*4882a593Smuzhiyun phy-names = "pcie-phy0", "pcie-phy1"; 560*4882a593Smuzhiyun}; 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun&extcon_usb1 { 563*4882a593Smuzhiyun vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; 564*4882a593Smuzhiyun}; 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun&extcon_usb2 { 567*4882a593Smuzhiyun vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; 568*4882a593Smuzhiyun}; 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun&m_can0 { 571*4882a593Smuzhiyun can-transceiver { 572*4882a593Smuzhiyun max-bitrate = <5000000>; 573*4882a593Smuzhiyun }; 574*4882a593Smuzhiyun}; 575*4882a593Smuzhiyun 576*4882a593Smuzhiyun&csi2_0 { 577*4882a593Smuzhiyun csi2_phy0: endpoint { 578*4882a593Smuzhiyun remote-endpoint = <&csi2_cam0>; 579*4882a593Smuzhiyun clock-lanes = <0>; 580*4882a593Smuzhiyun data-lanes = <1 2>; 581*4882a593Smuzhiyun }; 582*4882a593Smuzhiyun}; 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun&ipu2 { 585*4882a593Smuzhiyun status = "okay"; 586*4882a593Smuzhiyun memory-region = <&ipu2_cma_pool>; 587*4882a593Smuzhiyun}; 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun&ipu1 { 590*4882a593Smuzhiyun status = "okay"; 591*4882a593Smuzhiyun memory-region = <&ipu1_cma_pool>; 592*4882a593Smuzhiyun}; 593*4882a593Smuzhiyun 594*4882a593Smuzhiyun&dsp1 { 595*4882a593Smuzhiyun status = "okay"; 596*4882a593Smuzhiyun memory-region = <&dsp1_cma_pool>; 597*4882a593Smuzhiyun}; 598*4882a593Smuzhiyun 599*4882a593Smuzhiyun&dsp2 { 600*4882a593Smuzhiyun status = "okay"; 601*4882a593Smuzhiyun memory-region = <&dsp2_cma_pool>; 602*4882a593Smuzhiyun}; 603