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/OK3568_Linux_fs/u-boot/include/
H A Dmpc83xx.h24 #define EXC_OFF_SYS_RESET 0x0100
32 #define CONFIG_DEFAULT_IMMR 0xFF400000
35 #define IMMRBAR 0x0000
36 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
43 #define LBLAWBAR0 0x0020
44 #define LBLAWAR0 0x0024
45 #define LBLAWBAR1 0x0028
46 #define LBLAWAR1 0x002C
47 #define LBLAWBAR2 0x0030
48 #define LBLAWAR2 0x0034
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dls2080a_common.h21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
28 #define CONFIG_SYS_TEXT_BASE 0x80400000
30 #define CONFIG_SYS_TEXT_BASE 0x30100000
33 #define CONFIG_SYS_TEXT_BASE 0x20100000
34 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
35 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
36 #define CONFIG_ENV_SECT_SIZE 0x40000
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
54 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
56 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
[all …]
H A DT102xRDB.h38 #define CONFIG_SYS_TEXT_BASE 0x30001000
39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
40 #define CONFIG_SPL_PAD_TO 0x40000
41 #define CONFIG_SPL_MAX_SIZE 0x28000
42 #define RESET_VECTOR_OFFSET 0x27FFC
43 #define BOOT_PAGE_OFFSET 0x27000
52 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
53 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
65 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
[all …]
H A DT104xRDB.h26 #define CONFIG_SYS_TEXT_BASE 0x30001000
27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
28 #define CONFIG_SPL_PAD_TO 0x40000
29 #define CONFIG_SPL_MAX_SIZE 0x28000
35 #define RESET_VECTOR_OFFSET 0x27FFC
36 #define BOOT_PAGE_OFFSET 0x27000
50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
51 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
78 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43/
H A Ddma.h19 #define B43_DMA32_TXCTL 0x00
20 #define B43_DMA32_TXENABLE 0x00000001
21 #define B43_DMA32_TXSUSPEND 0x00000002
22 #define B43_DMA32_TXLOOPBACK 0x00000004
23 #define B43_DMA32_TXFLUSH 0x00000010
24 #define B43_DMA32_TXPARITYDISABLE 0x00000800
25 #define B43_DMA32_TXADDREXT_MASK 0x00030000
27 #define B43_DMA32_TXRING 0x04
28 #define B43_DMA32_TXINDEX 0x08
29 #define B43_DMA32_TXSTATUS 0x0C
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-sa1100/include/mach/
H A Dhardware.h17 #define UNCACHEABLE_ADDR 0xfa050000 /* ICIP */
31 #define VIO_BASE 0xf8000000 /* virtual start of IO space */
33 #define PIO_START 0x80000000 /* physical start of IO space */
36 IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
38 ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
/OK3568_Linux_fs/u-boot/board/hisilicon/poplar/
H A DREADME158 => tftp 0x30000000 fastboot.bin
161 scanning bus 0 for devices... 1 USB Device(s) found
164 scanning usb for storage devices... 0 Storage Device(s) found
170 Load address: 0x30000000
178 => mmc write 0x30000000 0 0x780
180 MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
190 => fatls usb 0:2
193 1 file(s), 0 dir(s)
195 => fatload usb 0:2 0x30000000 fastboot.bin
199 => mmc write 0x30000000 0 0x780
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/stm32/
H A Dst,mlahb.yaml61 reg = <0x10000000 0x40000>;
63 dma-ranges = <0x00000000 0x38000000 0x10000>,
64 <0x10000000 0x10000000 0x60000>,
65 <0x30000000 0x30000000 0x60000>;
68 reg = <0x10000000 0x40000>;
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphytbl_lcn.c10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dspear300.dtsi15 ranges = <0x60000000 0x60000000 0x50000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0x99000000 0x1000>;
25 reg = <0x60000000 0x1000>;
34 reg = <0x94000000 0x1000 /* FSMC Register */
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
44 reg = <0x70000000 0x100>;
49 shirq: interrupt-controller@0x50000000 {
[all …]
H A Dspear310.dtsi15 ranges = <0x40000000 0x40000000 0x10000000
16 0xb0000000 0xb0000000 0x10000000
17 0xd0000000 0xd0000000 0x30000000>;
21 reg = <0xb4000000 0x1000>;
29 reg = <0x44000000 0x1000 /* FSMC Register */
30 0x40000000 0x0010 /* NAND Base DATA */
31 0x40020000 0x0010 /* NAND Base ADDR */
32 0x40010000 0x0010>; /* NAND Base CMD */
37 shirq: interrupt-controller@0xb4000000 {
39 reg = <0xb4000000 0x1000>;
[all …]
H A Dspear3xx.dtsi14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0 0x40000000>;
32 ranges = <0xd0000000 0xd0000000 0x30000000>;
37 reg = <0xf1100000 0x1000>;
43 reg = <0xfc400000 0x1000>;
51 reg = <0xe0800000 0x8000>;
62 reg = <0xfc000000 0x1000>;
69 reg = <0xd0100000 0x1000>;
72 #size-cells = <0>;
[all …]
H A Dspear320.dtsi15 ranges = <0x40000000 0x40000000 0x80000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0xb3000000 0x1000>;
26 reg = <0x90000000 0x1000>;
36 reg = <0x4c000000 0x1000 /* FSMC Register */
37 0x50000000 0x0010 /* NAND Base DATA */
38 0x50020000 0x0010 /* NAND Base ADDR */
39 0x50010000 0x0010>; /* NAND Base CMD */
46 reg = <0x70000000 0x100>;
52 shirq: interrupt-controller@0xb3000000 {
[all …]
/OK3568_Linux_fs/u-boot/board/varisys/cyrus/
H A Dcyrus.c27 #define GPIO_OPENDRAIN 0x30000000
28 #define GPIO_DIR 0x3c000004
29 #define GPIO_INITIAL 0x30000000
30 #define GPIO_VGA_SWITCH 0x00001000
36 return 0; in checkboard()
49 setbits_be32(&gur->ddrclkdr, 0x001B001B); in board_early_init_f()
58 return 0; in board_early_init_f()
65 out_be32(&lbc->lbcr, 0); in board_early_init_r()
67 out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR); in board_early_init_r()
75 return 0; in board_early_init_r()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Drcar-pci.txt55 reg = <0 0xfe000000 0 0x80000>;
58 bus-range = <0x00 0xff>;
60 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
61 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
62 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
63 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
64 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
65 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
66 interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
68 interrupt-map-mask = <0 0 0 0>;
[all …]
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/firmware/
H A Dnvidia,tegra186-bpmp.txt76 reg = <0x0 0x30000000 0x0 0x50000>;
79 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
83 reg = <0x0 0x4e000 0x0 0x1000>;
88 reg = <0x0 0x4f000 0x0 0x1000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.txt75 reg = <0x0 0x30000000 0x0 0x50000>;
78 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
82 reg = <0x0 0x4e000 0x0 0x1000>;
89 reg = <0x0 0x4f000 0x0 0x1000>;
/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Dreg_booke.h26 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
54 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
55 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
56 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
57 #define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */
58 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
59 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
60 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
61 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
62 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3399-sdram-lpddr4-100.dtsi6 0x2
7 0xa
8 0x3
9 0x2
10 0x1
11 0x0
12 0xf
13 0xf
14 0
15 0
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/
H A Dbcm-sf2-eth-gmac.h16 #define GMAC0_REG_BASE 0x18042000
18 #define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020)
19 #define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100)
20 #define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188)
23 #define GMAC_DMA_PTR_OFFSET 0x04
24 #define GMAC_DMA_ADDR_LOW_OFFSET 0x08
25 #define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c
26 #define GMAC_DMA_STATUS0_OFFSET 0x10
27 #define GMAC_DMA_STATUS1_OFFSET 0x14
29 #define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200)
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dfsl_lbc.h19 #define BR0 0x5000 /* Register offset to immr */
20 #define BR1 0x5008
21 #define BR2 0x5010
22 #define BR3 0x5018
23 #define BR4 0x5020
24 #define BR5 0x5028
25 #define BR6 0x5030
26 #define BR7 0x5038
28 #define BR_BA 0xFFFF8000
30 #define BR_XBA 0x00006000
[all …]

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