1*4882a593Smuzhiyun* Renesas R-Car PCIe interface 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyuncompatible: "renesas,pcie-r8a7742" for the R8A7742 SoC; 5*4882a593Smuzhiyun "renesas,pcie-r8a7743" for the R8A7743 SoC; 6*4882a593Smuzhiyun "renesas,pcie-r8a7744" for the R8A7744 SoC; 7*4882a593Smuzhiyun "renesas,pcie-r8a774a1" for the R8A774A1 SoC; 8*4882a593Smuzhiyun "renesas,pcie-r8a774b1" for the R8A774B1 SoC; 9*4882a593Smuzhiyun "renesas,pcie-r8a774c0" for the R8A774C0 SoC; 10*4882a593Smuzhiyun "renesas,pcie-r8a7779" for the R8A7779 SoC; 11*4882a593Smuzhiyun "renesas,pcie-r8a7790" for the R8A7790 SoC; 12*4882a593Smuzhiyun "renesas,pcie-r8a7791" for the R8A7791 SoC; 13*4882a593Smuzhiyun "renesas,pcie-r8a7793" for the R8A7793 SoC; 14*4882a593Smuzhiyun "renesas,pcie-r8a7795" for the R8A7795 SoC; 15*4882a593Smuzhiyun "renesas,pcie-r8a7796" for the R8A77960 SoC; 16*4882a593Smuzhiyun "renesas,pcie-r8a77961" for the R8A77961 SoC; 17*4882a593Smuzhiyun "renesas,pcie-r8a77980" for the R8A77980 SoC; 18*4882a593Smuzhiyun "renesas,pcie-r8a77990" for the R8A77990 SoC; 19*4882a593Smuzhiyun "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or 20*4882a593Smuzhiyun RZ/G1 compatible device. 21*4882a593Smuzhiyun "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 or 22*4882a593Smuzhiyun RZ/G2 compatible device. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun When compatible with the generic version, nodes must list the 25*4882a593Smuzhiyun SoC-specific version corresponding to the platform first 26*4882a593Smuzhiyun followed by the generic version. 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun- reg: base address and length of the PCIe controller registers. 29*4882a593Smuzhiyun- #address-cells: set to <3> 30*4882a593Smuzhiyun- #size-cells: set to <2> 31*4882a593Smuzhiyun- bus-range: PCI bus numbers covered 32*4882a593Smuzhiyun- device_type: set to "pci" 33*4882a593Smuzhiyun- ranges: ranges for the PCI memory and I/O regions. 34*4882a593Smuzhiyun- dma-ranges: ranges for the inbound memory regions. 35*4882a593Smuzhiyun- interrupts: two interrupt sources for MSI interrupts, followed by interrupt 36*4882a593Smuzhiyun source for hardware related interrupts (e.g. link speed change). 37*4882a593Smuzhiyun- #interrupt-cells: set to <1> 38*4882a593Smuzhiyun- interrupt-map-mask and interrupt-map: standard PCI properties 39*4882a593Smuzhiyun to define the mapping of the PCIe interface to interrupt numbers. 40*4882a593Smuzhiyun- clocks: from common clock binding: clock specifiers for the PCIe controller 41*4882a593Smuzhiyun and PCIe bus clocks. 42*4882a593Smuzhiyun- clock-names: from common clock binding: should be "pcie" and "pcie_bus". 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunOptional properties: 45*4882a593Smuzhiyun- phys: from common PHY binding: PHY phandle and specifier (only make sense 46*4882a593Smuzhiyun for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks). 47*4882a593Smuzhiyun- phy-names: from common PHY binding: should be "pcie". 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunExample: 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunSoC-specific DT Entry: 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun pcie: pcie@fe000000 { 54*4882a593Smuzhiyun compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; 55*4882a593Smuzhiyun reg = <0 0xfe000000 0 0x80000>; 56*4882a593Smuzhiyun #address-cells = <3>; 57*4882a593Smuzhiyun #size-cells = <2>; 58*4882a593Smuzhiyun bus-range = <0x00 0xff>; 59*4882a593Smuzhiyun device_type = "pci"; 60*4882a593Smuzhiyun ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 61*4882a593Smuzhiyun 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 62*4882a593Smuzhiyun 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 63*4882a593Smuzhiyun 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 64*4882a593Smuzhiyun dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000 65*4882a593Smuzhiyun 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; 66*4882a593Smuzhiyun interrupts = <0 116 4>, <0 117 4>, <0 118 4>; 67*4882a593Smuzhiyun #interrupt-cells = <1>; 68*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 69*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic 0 116 4>; 70*4882a593Smuzhiyun clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>; 71*4882a593Smuzhiyun clock-names = "pcie", "pcie_bus"; 72*4882a593Smuzhiyun }; 73