Lines Matching +full:0 +full:x30000000
38 #define CONFIG_SYS_TEXT_BASE 0x30001000
39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
40 #define CONFIG_SPL_PAD_TO 0x40000
41 #define CONFIG_SPL_MAX_SIZE 0x28000
42 #define RESET_VECTOR_OFFSET 0x27FFC
43 #define BOOT_PAGE_OFFSET 0x27000
52 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
53 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
65 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
84 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
87 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
88 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
105 #define CONFIG_SYS_TEXT_BASE 0xeff40000
109 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
139 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
146 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
147 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
151 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
153 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
155 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
157 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
158 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
163 #define CONFIG_ENV_SPI_BUS 0
164 #define CONFIG_ENV_SPI_CS 0
166 #define CONFIG_ENV_SPI_MODE 0
167 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
168 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
170 #define CONFIG_ENV_SECT_SIZE 0x10000
172 #define CONFIG_ENV_SECT_SIZE 0x40000
176 #define CONFIG_SYS_MMC_ENV_DEV 0
177 #define CONFIG_ENV_SIZE 0x2000
178 #define CONFIG_ENV_OFFSET (512 * 0x800)
181 #define CONFIG_ENV_SIZE 0x2000
188 #define CONFIG_ENV_ADDR 0xffe20000
189 #define CONFIG_ENV_SIZE 0x2000
191 #define CONFIG_ENV_SIZE 0x2000
194 #define CONFIG_ENV_SIZE 0x2000
195 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
216 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
219 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
220 #define CONFIG_SYS_MEMTEST_END 0x00400000
226 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
238 #define CONFIG_SYS_DCSRBAR 0xf0000000
239 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
245 #define CONFIG_SYS_EEPROM_BUS_NUM 0
246 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
255 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
262 #define CONFIG_SYS_SPD_BUS_NUM 0
263 #define SPD_EEPROM_ADDRESS 0x51
273 #define CONFIG_SYS_FLASH_BASE 0xe8000000
275 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
280 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
291 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
294 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
295 FTIM0_NOR_TEADC(0x5) | \
296 FTIM0_NOR_TEAHC(0x5))
297 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
298 FTIM1_NOR_TRAD_NOR(0x1A) |\
299 FTIM1_NOR_TSEQRAD_NOR(0x13))
300 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
301 FTIM2_NOR_TCH(0x4) | \
302 FTIM2_NOR_TWPH(0x0E) | \
303 FTIM2_NOR_TWP(0x1c))
304 #define CONFIG_SYS_NOR_FTIM3 0x0
319 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
320 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
321 #define CONFIG_SYS_CSPR2_EXT (0xf)
327 #define CONFIG_SYS_CSOR2 0x0
330 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
331 FTIM0_GPCM_TEADC(0x0e) | \
332 FTIM0_GPCM_TEAHC(0x0e))
333 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
334 FTIM1_GPCM_TRAD(0x1f))
335 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
336 FTIM2_GPCM_TCH(0x8) | \
337 FTIM2_GPCM_TWP(0x1f))
338 #define CONFIG_SYS_CS2_FTIM3 0x0
343 #define CONFIG_SYS_NAND_BASE 0xff800000
345 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
349 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
378 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
379 FTIM0_NAND_TWP(0x18) | \
380 FTIM0_NAND_TWCHT(0x07) | \
381 FTIM0_NAND_TWH(0x0a))
382 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
383 FTIM1_NAND_TWBE(0x39) | \
384 FTIM1_NAND_TRR(0x0e) | \
385 FTIM1_NAND_TRP(0x18))
386 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
387 FTIM2_NAND_TREH(0x0a) | \
388 FTIM2_NAND_TWHRE(0x1e))
389 #define CONFIG_SYS_NAND_FTIM3 0x0
449 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
462 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
475 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
480 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
481 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
482 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
483 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
488 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
503 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
505 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
506 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
507 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
510 #define I2C_PCA6408_ADDR 0x20
513 #define I2C_MUX_CH_DEFAULT 0x8
520 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
527 #define CONFIG_SF_DEFAULT_MODE 0
531 * Memory space is mapped 1-1, but I/O space must start from 0.
546 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
548 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
549 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
551 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
552 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
554 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
555 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
556 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
558 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
560 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
562 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
567 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
569 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
570 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
572 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
573 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
575 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
576 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
577 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
579 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
581 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
583 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
588 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
590 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
591 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
593 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
594 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
596 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
597 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
598 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
600 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
602 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
604 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
609 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
611 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
612 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
614 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
615 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
617 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
618 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
619 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
621 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
623 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
625 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
653 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
655 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
659 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
660 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
661 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
667 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
669 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
671 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
675 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
676 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
677 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
683 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
694 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
695 * env, so we got 0x110000.
698 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
699 #define CONFIG_SYS_QE_FW_ADDR 0x130000
702 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
704 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
707 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
708 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
727 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
730 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
731 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
733 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
734 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
743 #define RGMII_PHY1_ADDR 0x2
744 #define RGMII_PHY2_ADDR 0x6
745 #define SGMII_AQR_PHY_ADDR 0x2
746 #define FM1_10GEC1_PHY_ADDR 0x1
748 #define RGMII_PHY1_ADDR 0x1
749 #define SGMII_RTK_PHY_ADDR 0x3
750 #define SGMII_AQR_PHY_ADDR 0x2
768 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
784 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
817 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
818 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
819 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
821 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
822 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
823 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
824 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
825 "netdev=eth0\0" \
831 "cmp.b $loadaddr $ubootaddr $filesize\0" \
832 "consoledev=ttyS0\0" \
833 "ramdiskaddr=2000000\0" \
834 "fdtaddr=1e00000\0" \
835 "bdev=sda3\0"
840 "setenv ramdiskaddr 0x02000000;" \
841 "setenv fdtaddr 0x00c00000;" \
842 "setenv loadaddr 0x1000000;" \