1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#" 5*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: STMicroelectronics STM32 ML-AHB interconnect bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Fabien Dessenne <fabien.dessenne@st.com> 11*4882a593Smuzhiyun - Arnaud Pouliquen <arnaud.pouliquen@st.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects 15*4882a593Smuzhiyun a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory 16*4882a593Smuzhiyun parts can be accessed through different addresses (see "RAM aliases" in [1]) 17*4882a593Smuzhiyun using different buses (see [2]): balancing the Cortex-M firmware accesses 18*4882a593Smuzhiyun among those ports allows to tune the system performance. 19*4882a593Smuzhiyun [1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf 20*4882a593Smuzhiyun [2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunallOf: 23*4882a593Smuzhiyun - $ref: /schemas/simple-bus.yaml# 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunproperties: 26*4882a593Smuzhiyun compatible: 27*4882a593Smuzhiyun contains: 28*4882a593Smuzhiyun enum: 29*4882a593Smuzhiyun - st,mlahb 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun dma-ranges: 32*4882a593Smuzhiyun description: | 33*4882a593Smuzhiyun Describe memory addresses translation between the local CPU and the 34*4882a593Smuzhiyun remote Cortex-M processor. Each memory region, is declared with 35*4882a593Smuzhiyun 3 parameters: 36*4882a593Smuzhiyun - param 1: device base address (Cortex-M processor address) 37*4882a593Smuzhiyun - param 2: physical base address (local CPU address) 38*4882a593Smuzhiyun - param 3: size of the memory region. 39*4882a593Smuzhiyun maxItems: 3 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun '#address-cells': 42*4882a593Smuzhiyun const: 1 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun '#size-cells': 45*4882a593Smuzhiyun const: 1 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunrequired: 48*4882a593Smuzhiyun - compatible 49*4882a593Smuzhiyun - '#address-cells' 50*4882a593Smuzhiyun - '#size-cells' 51*4882a593Smuzhiyun - dma-ranges 52*4882a593Smuzhiyun 53*4882a593SmuzhiyununevaluatedProperties: false 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunexamples: 56*4882a593Smuzhiyun - | 57*4882a593Smuzhiyun mlahb: ahb@38000000 { 58*4882a593Smuzhiyun compatible = "st,mlahb", "simple-bus"; 59*4882a593Smuzhiyun #address-cells = <1>; 60*4882a593Smuzhiyun #size-cells = <1>; 61*4882a593Smuzhiyun reg = <0x10000000 0x40000>; 62*4882a593Smuzhiyun ranges; 63*4882a593Smuzhiyun dma-ranges = <0x00000000 0x38000000 0x10000>, 64*4882a593Smuzhiyun <0x10000000 0x10000000 0x60000>, 65*4882a593Smuzhiyun <0x30000000 0x30000000 0x60000>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun m4_rproc: m4@10000000 { 68*4882a593Smuzhiyun reg = <0x10000000 0x40000>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun... 73