Lines Matching +full:0 +full:x30000000
21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
28 #define CONFIG_SYS_TEXT_BASE 0x80400000
30 #define CONFIG_SYS_TEXT_BASE 0x30100000
33 #define CONFIG_SYS_TEXT_BASE 0x20100000
34 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
35 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
36 #define CONFIG_ENV_SECT_SIZE 0x40000
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
54 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
56 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
66 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
68 * DDR controller use 0 as the base address for binding.
71 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
79 * will be udpated later when get_bus_freq(0) is available.
106 * During booting, IFC is mapped at the region of 0x30000000.
109 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
110 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
111 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
115 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
116 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
117 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
118 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
119 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
121 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
125 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
128 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
129 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
130 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
132 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
133 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
139 #define QIXIS_BASE_PHYS 0x20000000
140 #define QIXIS_BASE_PHYS_EARLY 0xC000000
141 #define QIXIS_STAT_PRES1 0xb
142 #define QIXIS_SDID_MASK 0x07
143 #define QIXIS_ESDHC_NO_ADAPTER 0x7
145 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
146 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
150 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
151 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
152 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
153 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
155 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
156 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
176 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
192 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
193 "loadaddr=0x80100000\0" \
194 "kernel_addr=0x100000\0" \
195 "ramdisk_addr=0x800000\0" \
196 "ramdisk_size=0x2000000\0" \
197 "fdt_high=0xa0000000\0" \
198 "initrd_high=0xffffffffffffffff\0" \
199 "kernel_start=0x581000000\0" \
200 "kernel_load=0xa0000000\0" \
201 "kernel_size=0x2800000\0" \
202 "console=ttyAMA0,38400n8\0" \
203 "mcinitcmd=fsl_mc start mc 0x580a00000" \
204 " 0x580e00000 \0"
207 #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
208 " fsl_mc apply dpl 0x80200000 &&" \
212 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
224 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
225 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
227 #define CONFIG_SPL_MAX_SIZE 0x16000
228 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
230 #define CONFIG_SPL_TEXT_BASE 0x1800a000
233 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
236 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
237 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000