| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3506.c | 24 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
188 u32 sel, con, div; in rk3506_armclk_get_rate() local
212 u32 con, sel, div, old_div; in rk3506_armclk_set_rate() local
273 u32 con, div; in rk3506_pll_div_get_rate() local
308 u32 div; in rk3506_pll_div_set_rate() local
345 u32 sel, con, div; in rk3506_bus_get_rate() local
384 u32 sel, div; in rk3506_bus_set_rate() local
427 u32 sel, con, div; in rk3506_peri_get_rate() local
461 u32 sel, div; in rk3506_peri_set_rate() local
498 u32 sel, con, div; in rk3506_sdmmc_get_rate() local
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| H A D | clk_rv1108.c | 29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
66 const struct pll_div *div) in rkclk_set_pll()
147 uint8_t div; in rv1108_mac_set_clk() local
172 u32 div; in rv1108_sfc_set_clk() local
191 u32 div, val; in rv1108_saradc_get_clk() local
216 u32 div, val; in rv1108_aclk_vio1_get_clk() local
242 u32 div, val; in rv1108_aclk_vio0_get_clk() local
277 u32 div, val; in rv1108_dclk_vop_get_clk() local
305 u32 div, val; in rv1108_aclk_bus_get_clk() local
333 u32 div, val; in rv1108_aclk_peri_get_clk() local
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| H A D | clk_rk3562.c | 20 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
205 u32 sel, con, div; in rk3562_bus_get_rate() local
240 u32 sel, div; in rk3562_bus_set_rate() local
279 u32 sel, con, div; in rk3562_peri_get_rate() local
314 u32 sel, div; in rk3562_peri_set_rate() local
353 u32 sel, con, div; in rk3562_i2c_get_rate() local
397 u32 sel, div; in rk3562_i2c_set_rate() local
447 u32 reg, con, fracdiv, div, src, p_src, p_rate; in rk3562_uart_get_rate() local
525 u32 reg, clk_src, uart_src, div; in rk3562_uart_set_rate() local
626 u32 sel, con, div, mask, shift; in rk3562_pwm_get_rate() local
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| H A D | clk_rk3588.c | 22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
286 u32 con, sel, div, rate, prate; in rk3588_top_get_clk() local
656 u32 div, sel, con, prate; in rk3588_adc_get_clk() local
747 u32 sel, con, div, prate; in rk3588_mmc_get_clk() local
815 int src_clk, div; in rk3588_mmc_set_clk() local
901 u32 div, con, parent; in rk3588_aux16m_get_clk() local
922 u32 div; in rk3588_aux16m_set_clk() local
950 u32 div, sel, con, parent; in rk3588_aclk_vop_get_clk() local
1001 int src_clk, div; in rk3588_aclk_vop_set_clk() local
1064 u32 div, sel, con, parent; in rk3588_dclk_vop_get_clk() local
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| H A D | clk_rk3576.c | 22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
172 u32 con, sel, div, rate; in rk3576_bus_get_clk() local
278 u32 con, sel, div, rate, prate; in rk3576_top_get_clk() local
694 u32 div, sel, con, prate; in rk3576_adc_get_clk() local
765 u32 sel, con, prate, div = 0; in rk3576_mmc_get_clk() local
863 int src_clk, div = 0; in rk3576_mmc_set_clk() local
972 u32 div, sel, con, parent = 0; in rk3576_aclk_vop_get_clk() local
1047 int src_clk, div; in rk3576_aclk_vop_set_clk() local
1131 u32 div, sel, con, parent; in rk3576_dclk_vop_get_clk() local
1177 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; in rk3576_dclk_vop_set_clk() local
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| H A D | clk_rk3328.c | 25 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
170 u32 div, con; in rk3328_i2c_get_clk() local
262 u8 div; in rk3328_gmac2io_set_clk() local
286 u8 div; in rk3328_gmac2phy_src_set_clk() local
319 u32 div, con, con_id; in rk3328_mmc_get_clk() local
387 u32 div, con, mux, p_rate; in rk3328_spi_get_clk() local
403 u32 div = priv->gpll_hz / hz; in rk3328_spi_set_clk() local
417 u32 div, con; in rk3328_pwm_get_clk() local
428 u32 div = priv->gpll_hz / hz; in rk3328_pwm_set_clk() local
441 u32 div, val; in rk3328_saradc_get_clk() local
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| H A D | clk_rv1126.c | 30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
217 u32 div, con; in rv1126_i2c_get_pmuclk() local
264 u32 div, sel, con; in rv1126_pwm_get_pmuclk() local
341 u32 div, con; in rv1126_spi_get_pmuclk() local
369 u32 div, con; in rv1126_pdpmu_get_pmuclk() local
599 u32 con, div; in rv1126_pdcore_get_clk() local
623 u32 con, div, sel, parent; in rv1126_pdbus_get_clk() local
717 u32 con, div, parent; in rv1126_pdphp_get_clk() local
769 u32 con, div; in rv1126_pdaudio_get_clk() local
794 u32 div, con; in rv1126_i2c_get_clk() local
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| H A D | clk_rk1808.c | 30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
98 u32 div, con; in rk1808_i2c_get_clk() local
191 u32 div, con, con_id; in rk1808_mmc_get_clk() local
271 u32 div, con; in rk1808_sfc_get_clk() local
297 u32 div, con; in rk1808_saradc_get_clk() local
324 u32 div, con; in rk1808_pwm_get_clk() local
386 u32 div, con; in rk1808_tsadc_get_clk() local
412 u32 div, con; in rk1808_spi_get_clk() local
475 u32 div, con, parent; in rk1808_vop_get_clk() local
600 u8 div; in rk1808_mac_set_clk() local
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| H A D | clk_rk3036.c | 47 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
63 const struct pll_div *div) in rkclk_set_pll()
246 uint div, mux; in rockchip_mmc_get_clk() local
338 u32 div, con; in rk3036_spi_get_clk() local
350 int div; in rk3036_spi_set_clk() local
364 u32 con, div, sel, parent; in rockchip_dclk_lcdc_get_clk() local
396 u32 con, div, sel, parent; in rockchip_aclk_lcdc_get_clk() local
429 u32 div, con, parent; in rk3036_peri_get_clk() local
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| H A D | clk_rk3128.c | 23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
144 uint div, mux; in rockchip_mmc_get_clk() local
226 u32 div, con, parent; in rk3128_peri_get_clk() local
307 u32 div, con, parent; in rk3128_bus_get_clk() local
377 u32 div, con, parent; in rk3128_spi_get_clk() local
389 int div; in rk3128_spi_set_clk() local
404 u32 div, val; in rk3128_saradc_get_clk() local
473 u32 div, con, parent; in rk3128_vop_get_rate() local
502 u32 div, val; in rk3128_crypto_get_rate() local
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| H A D | clk_rk3308.c | 29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
200 u32 div, con, con_id; in rk3308_i2c_get_clk() local
266 u8 div; in rk3308_mac_set_clk() local
310 u32 div, con, con_id; in rk3308_mmc_get_clk() local
384 u32 div, con; in rk3308_saradc_get_clk() local
412 u32 div, con; in rk3308_tsadc_get_clk() local
440 u32 div, con, con_id; in rk3308_spi_get_clk() local
499 u32 div, con; in rk3308_pwm_get_clk() local
528 u32 div, pll_sel, vol_sel, con, parent; in rk3308_vop_get_clk() local
565 u32 i, div, best_div = 0, best_sel = 0; in rk3308_vop_set_clk() local
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| H A D | clk_rk3528.c | 21 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
240 u32 div, mask, shift; in rk3528_ppll_matrix_get_rate() local
282 u32 id, div, mask, shift; in rk3528_ppll_matrix_set_rate() local
327 u32 sel, div, mask, shift, con; in rk3528_cgpll_matrix_get_rate() local
435 u32 sel, div, mask, shift, con; in rk3528_cgpll_matrix_set_rate() local
848 u32 div, con; in rk3528_adc_get_clk() local
878 u32 div, mask, shift; in rk3528_adc_set_clk() local
909 u32 div, sel, con; in rk3528_sdmmc_get_clk() local
932 u32 div, sel; in rk3528_sdmmc_set_clk() local
958 u32 div, sel, con, parent; in rk3528_sfc_get_clk() local
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| H A D | clk_rk3368.c | 62 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
141 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) in pll_para_config()
250 const struct pll_div *div) in rkclk_set_pll()
295 u32 div, con, con_id, rate; in rk3368_mmc_get_clk() local
358 u32 div = DIV_ROUND_UP(parent_rate, rate); in rk3368_mmc_find_best_rate_and_parent() local
390 u32 con_id, mux = 0, div = 0; in rk3368_mmc_set_clk() local
462 u8 div; in rk3368_gmac_set_clk() local
517 u32 div, val; in rk3368_spi_get_clk() local
565 u32 div, val; in rk3368_saradc_get_clk() local
590 u32 div, con, parent; in rk3368_bus_get_clk() local
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| H A D | clk_rk322x.c | 22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
145 uint div, mux; in rk322x_mmc_get_clk() local
195 u8 div; in rk322x_mac_set_clk() local
273 u32 div, con, parent; in rk322x_bus_get_clk() local
351 u32 div, con, parent; in rk322x_peri_get_clk() local
424 u32 div, con, parent; in rk322x_spi_get_clk() local
436 int div; in rk322x_spi_set_clk() local
451 u32 div, con, sel, parent; in rk322x_vop_get_clk() local
532 u32 div, con, parent; in rk322x_crypto_get_clk() local
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| H A D | clk_px30.c | 51 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
300 u32 div, con; in px30_i2c_get_clk() local
522 u32 div, con; in px30_nandc_get_clk() local
554 u32 div, con, con_id; in px30_mmc_get_clk() local
627 u32 div, con; in px30_sfc_get_clk() local
653 u32 div, con; in px30_pwm_get_clk() local
706 u32 div, con; in px30_saradc_get_clk() local
732 u32 div, con; in px30_tsadc_get_clk() local
758 u32 div, con; in px30_spi_get_clk() local
811 u32 div, con, parent; in px30_vop_get_clk() local
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| H A D | clk_rv1126b.c | 22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
354 u32 div, sel, con, prate; in rv1126b_mmc_get_clk() local
585 u32 sel, div, con; in rv1126b_pwm_get_clk() local
682 u32 sel, div, con; in rv1126b_adc_get_clk() local
1034 u32 con, div, src, p_rate; in rv1126b_uart_get_rate() local
1123 u32 uart_src, div, p_rate; in rv1126b_uart_set_rate() local
1325 u32 sel, div, con, p_rate; in rv1126b_vop_get_rate() local
1348 int src_clk, div, p_rate; in rv1126b_vop_set_rate() local
1375 u32 sel, div, con, p_rate; in rv1126b_mac_get_rate() local
1418 int src_clk, div, p_rate; in rv1126b_mac_set_rate() local
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| H A D | clk_rv1103b.c | 23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
65 u32 con, sel, div, rate, prate; in rv1103b_peri_get_clk() local
117 int src_clk, div; in rv1103b_peri_set_clk() local
276 u32 div, sel, con, prate; in rv1103b_mmc_get_clk() local
549 u32 div, con; in rv1103b_adc_get_clk() local
661 u32 reg, con, fracdiv, div, src, p_rate; in rv1103b_uart_get_rate() local
709 u32 reg, uart_src, div; in rv1103b_uart_set_rate() local
987 u32 div; in rv1103b_clk_init() local
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| /rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/ |
| H A D | clock.c | 138 unsigned long div; in s5pc110_get_arm_clk() local
158 unsigned long div; in s5pc100_get_arm_clk() local
181 uint div, d0_bus_ratio; in get_hclk() local
198 uint div, d1_bus_ratio, pclkd1_ratio; in get_pclkd1() local
219 unsigned int div; in get_hclk_sys() local
248 unsigned int div; in get_pclk_sys() local
324 void set_mmc_clk(int dev_index, unsigned int div) in set_mmc_clk()
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| /rk3399_rockchip-uboot/arch/arm/mach-at91/armv7/ |
| H A D | clock.c | 42 unsigned mul, div; in at91_pll_rate() local
153 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div) in at91_enable_periph_generated_clk()
219 u32 regval, clk_source, div; in at91_get_periph_generated_clk() local
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| /rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mxs/ |
| H A D | clock.c | 42 uint32_t clkctrl, clkseq, div; in mxs_get_pclk() local
74 uint32_t div; in mxs_get_hclk() local
92 uint32_t clkctrl, clkseq, div; in mxs_get_emiclk() local
123 uint32_t clkctrl, clkseq, div; in mxs_get_gpmiclk() local
149 uint32_t div; in mxs_set_ioclk() local
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| /rk3399_rockchip-uboot/drivers/video/drm/rk628/ |
| H A D | rk628_cru.c | 299 u32 mux, div = 0; in rk628_cru_clk_get_rate_sclk_vop() local
320 u32 mux = 0, div = 0; in rk628_cru_clk_get_rate_clk_imodet() local
362 u32 mux, div = 0; in rk628_cru_clk_get_rate_uart_src() local
410 u8 div; in rk628_cru_clk_set_rate_sclk_hdmirx_aud() local
432 u8 div = 0; in rk628_cru_clk_get_rate_sclk_hdmirx_aud() local
472 u32 div; in rk628_cru_clk_set_rate_bt1120_dec() local
484 u32 div = 0; in rk628_cru_clk_get_rate_bt1120_dec() local
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| /rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mx25/ |
| H A D | generic.c | 74 ulong div; in imx_get_armclk() local
90 ulong div; in imx_get_ahbclk() local
108 ulong div; in imx_get_perclk() local
120 ulong div = (fref + freq - 1) / freq; in imx_set_perclk() local
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| /rk3399_rockchip-uboot/arch/arm/mach-imx/mx7/ |
| H A D | clock_slice.c | 521 int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div) in clock_set_postdiv()
549 int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div) in clock_get_postdiv()
573 int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div, in clock_set_autopostdiv()
611 int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div, in clock_get_autopostdiv()
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| /rk3399_rockchip-uboot/arch/arm/mach-davinci/ |
| H A D | cpu.c | 118 u32 div; in pll_div() local
149 static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) in pll_sysclk_mhz()
179 unsigned int davinci_clk_get(unsigned int div) in davinci_clk_get()
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| /rk3399_rockchip-uboot/arch/arm/mach-exynos/ |
| H A D | clock.c | 117 unsigned int div; in exynos_get_pll_clk() local
369 unsigned int src = 0, div = 0, sub_div = 0; in exynos5_get_periph_rate() local
468 unsigned int src = 0, div = 0, sub_div = 0; in exynos542x_get_periph_rate() local
574 unsigned long div; in exynos4_get_arm_clk() local
596 unsigned long div; in exynos4x12_get_arm_clk() local
618 unsigned long div; in exynos5_get_arm_clk() local
834 static void exynos4_set_mmc_clk(int dev_index, unsigned int div) in exynos4_set_mmc_clk()
869 static void exynos5_set_mmc_clk(int dev_index, unsigned int div) in exynos5_set_mmc_clk()
893 static void exynos5420_set_mmc_clk(int dev_index, unsigned int div) in exynos5420_set_mmc_clk()
1347 unsigned int div; in exynos5_set_i2s_clk_prescaler() local
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