22 #define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))  argument
286 	u32 con, sel, div, rate, prate;  in rk3588_top_get_clk()  local
656 	u32 div, sel, con, prate;  in rk3588_adc_get_clk()  local
747 	u32 sel, con, div, prate;  in rk3588_mmc_get_clk()  local
815 	int src_clk, div;  in rk3588_mmc_set_clk()  local
901 	u32 div, con, parent;  in rk3588_aux16m_get_clk()  local
922 	u32 div;  in rk3588_aux16m_set_clk()  local
950 	u32 div, sel, con, parent;  in rk3588_aclk_vop_get_clk()  local
1001 	int src_clk, div;  in rk3588_aclk_vop_set_clk()  local
1064 	u32 div, sel, con, parent;  in rk3588_dclk_vop_get_clk()  local
1114 	u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;  in rk3588_dclk_vop_set_clk()  local
1226 	u32 div, sel, con, parent;  in rk3588_clk_csihost_get_clk()  local
1257 	u32 con, div;  in rk3588_gmac_get_clk()  local
1285 	int div;  in rk3588_gmac_set_clk()  local
1325 	u32 reg, con, fracdiv, div, src, p_src, p_rate;  in rk3588_uart_get_rate()  local
1387 	u32 reg, clk_src, uart_src, div;  in rk3588_uart_set_rate()  local
1462 	u32 con, div, src;  in rk3588_pciephy_get_rate()  local
1497 	u32 clk_src, div;  in rk3588_pciephy_set_rate()  local
2062 	int ret, div;  in rk3588_clk_init()  local
2246 #define CLKDIV_6BITS_SHF(div, shift)	BITS_WITH_WMASK(div, 0x3fU, shift)  argument
2247 #define CLKDIV_5BITS_SHF(div, shift)	BITS_WITH_WMASK(div, 0x1fU, shift)  argument
2251 	u32 src, div;  in rk3588_clk_scmi_get_rate()  local
2356 	u32 src, div;  in rk3588_clk_scmi_set_rate()  local