| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | asm_macros.S | 19 #define TLB_INVALIDATE(_reg, _coproc) \ argument
24 #define TLB_INVALIDATE(_reg, _coproc) \ argument
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| /rk3399_ARM-atf/plat/xilinx/common/include/ |
| H A D | plat_common.h | 12 #define FIELD_GET(_mask, _reg) \ argument
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| /rk3399_ARM-atf/include/drivers/cadence/ |
| H A D | cdns_nand.h | 15 #define FIELD_GET(_mask, _reg) \ argument
134 #define CNF_CMDREG(_reg) (CNF_CMDREG_REG_BASE \ argument
186 #define CNF_CTRLCFG(_reg) (CNF_CTRLCFG_REG_BASE \ argument
200 #define CNF_DI(_reg) (CNF_DI_REG_BASE \ argument
222 #define CNF_CTRLPARAM(_reg) (CNF_CTRLPARAM_REG_BASE \ argument
234 #define CNF_PROT(_reg) (CNF_PROT_REG_BASE \ argument
327 #define CNF_MINICTRL(_reg) (CNF_MINICTRL_REG_BASE \ argument
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| H A D | cdns_combo_phy.h | 143 #define CP_DLL(_reg) (CP_DLL_REG_BASE \ argument
158 #define CP_CTB(_reg) (CP_CTB_REG_BASE \ argument
206 #define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ argument
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| H A D | cdns_sdmmc.h | 339 #define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ argument
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| /rk3399_ARM-atf/plat/intel/soc/common/include/ |
| H A D | socfpga_system_manager.h | 33 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ argument
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| H A D | socfpga_noc.h | 21 #define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \ argument
24 #define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \ argument
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| H A D | socfpga_f2sdram_manager.h | 45 #define SOCFPGA_F2SDRAMMGR(_reg) (SOCFPGA_F2SDRAMMGR_REG_BASE \ argument
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| H A D | socfpga_reset_manager.h | 233 #define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE + (SOCFPGA_RSTMGR_##_reg)) argument
234 #define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field) argument
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/include/ |
| H A D | agilex5_clock_manager.h | 26 #define CLKMGR(_reg) (CLKMGR_BASE + (CLKMGR_##_reg)) argument
60 #define CLKMGR_MAINPLL(_reg) (CLKMGR_MAINPLL_BASE + \ argument
90 #define CLKMGR_PERPLL(_reg) (CLKMGR_PERPLL_BASE + \ argument
112 #define CLKMGR_ALTERA(_reg) (CLKMGR_ALTERA_BASE + \ argument
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| H A D | agilex5_power_manager.h | 82 #define AGX5_PWRMGR(_reg) (AGX5_PWRMGR_BASE + \ argument
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| H A D | agilex5_pinmux.h | 140 #define SOCFPGA_PINUMX_USEFPGA(_reg) (AGX5_PINMUX_EMAC0_USEFPGA \ argument
195 #define SOCFPGA_PINMUX(_reg) (SOCFPGA_PINMUX_REG_BASE \ argument
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| H A D | agilex5_system_manager.h | 236 #define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \ argument
238 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ argument
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| H A D | agilex5_iossm_mailbox.h | 18 #define FIELD_GET(_mask, _reg) \ argument
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| H A D | agilex5_memory_controller.h | 172 #define SOCFPGA_MEMCTRL(_reg) (SOCFPGA_MEMCTRL_REG_BASE \ argument
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/include/ |
| H A D | s10_system_manager.h | 198 #define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \ argument
201 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ argument
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| /rk3399_ARM-atf/plat/intel/soc/agilex/include/ |
| H A D | agilex_system_manager.h | 199 #define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \ argument
202 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ argument
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| H A D | agilex_memory_controller.h | 172 #define SOCFPGA_MEMCTRL(_reg) (SOCFPGA_MEMCTRL_REG_BASE \ argument
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| /rk3399_ARM-atf/plat/intel/soc/n5x/include/ |
| H A D | n5x_system_manager.h | 202 #define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \ argument
205 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ argument
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| /rk3399_ARM-atf/plat/imx/imx8ulp/scmi/ |
| H A D | scmi_pd.c | 138 #define PWR_DOMAIN(_name, _reg, _psw_parent, _sram_parent, \ argument
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| /rk3399_ARM-atf/drivers/st/clk/ |
| H A D | clk-stm32mp13.c | 1186 #define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\ argument
1676 #define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\ argument
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| H A D | clk-stm32mp2.c | 711 #define CLK_PLL_CFG(_idx, _clk_id, _reg)\ argument
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