feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework

This commit introduces linker changes for NUMA aware per-cpu objects in
the BL31 and BL32 images. The per-cpu framework is de

feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework

This commit introduces linker changes for NUMA aware per-cpu objects in
the BL31 and BL32 images. The per-cpu framework is designed to minimise
cache thrashing, and the linker layout ensures each CPU’s per-cpu data
is placed on a separate cache line. This isolation is expected to
improve performance when the per-cpu framework is enabled.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ie4d8b4e444971adbd9dba0446d1ab8cafaca1556

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docs(changelog): add scope for per-cpu framework

define "per-cpu" as the scope to be used for any changes to per-cpu
framework.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I076eda

docs(changelog): add scope for per-cpu framework

define "per-cpu" as the scope to be used for any changes to per-cpu
framework.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I076eda00f2aeab2e22dec0e1d7e3687737473848

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feat(el3-runtime): add flags argument to handle_sysreg_trap

Extend handle_sysreg_trap() to accept an additional flags
parameter indicating the caller’s security state.
The EL3 synchronous exception

feat(el3-runtime): add flags argument to handle_sysreg_trap

Extend handle_sysreg_trap() to accept an additional flags
parameter indicating the caller’s security state.
The EL3 synchronous exception handler now passes this value
when dispatching trapped system register accesses.
This allows handle_sysreg_trap() to handle traps based on
the originating security context.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ic6e4a13297bf0b3afec3b83e1696c03286615560

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fix(cpufeat): remove unused FEAT_NV feature functions

The FEAT_NV feature functions were introduced in a8d5d3d54
but never used. This patch cleans up this dead code.

Signed-off-by: Arvind Ram Praka

fix(cpufeat): remove unused FEAT_NV feature functions

The FEAT_NV feature functions were introduced in a8d5d3d54
but never used. This patch cleans up this dead code.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I05fae1bd187782e5de6074a7b265fcdd4b473a68

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Merge changes from topic "mp/misc_fixes" into integration

* changes:
chore: ignore memory src pycache
fix(fvp): skip SP discovery through FFA_PARTITION_INFO_GET_REGS

fix(rmm): enable SMCCC_ARCH_FEATURE_AVAILABILITY for RMM

Always enable SMCCC_ARCH_FEATURE_AVAILABILITY when the
ENABLE_RME flag is set.

Change-Id: I9632d7100aace1537a931b452a9140d014871130
Signed-o

fix(rmm): enable SMCCC_ARCH_FEATURE_AVAILABILITY for RMM

Always enable SMCCC_ARCH_FEATURE_AVAILABILITY when the
ENABLE_RME flag is set.

Change-Id: I9632d7100aace1537a931b452a9140d014871130
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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Merge changes I54152fbb,I9b70c3a2 into integration

* changes:
feat(cpufeat): introduce FEAT_RME_GDI support
feat(cpufeat): add support for FEAT_RME_GPC2

fix(versal2): align comment about invalid console selection

Error message should be aligned actual symbol used for console section
which has been changed by commit 2333ab4cd214 ("fix(versal2): renam

fix(versal2): align comment about invalid console selection

Error message should be aligned actual symbol used for console section
which has been changed by commit 2333ab4cd214 ("fix(versal2): rename
console build arg to generic").

Change-Id: I230892875a6343ca8ffc55e0fac251f6586cf3f4
Signed-off-by: Michal Simek <michal.simek@amd.com>

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docs(cpufeat): add a checklist on how to add a feature

Adding features is an arcane job with a long list of things to consider.
There is no single place to list these things so someone new to this
m

docs(cpufeat): add a checklist on how to add a feature

Adding features is an arcane job with a long list of things to consider.
There is no single place to list these things so someone new to this
must be guided along, usually at code review. Further, the process
changes occasionally so it can be difficult even for an experienced
contributor to get right.

So add a checklist along with brief explanations on what to look for so
we can make our job nicer.

Change-Id: I09dd0062b742c9fce5a8f86a2067adc941db6899
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "lfa-prime-error-handling" into integration

* changes:
feat(lfa): introduce support for call_again for LFA_PRIME
feat(lfa): allow LFA_PRIME from one CPU at a time

feat(cpufeat): introduce FEAT_RME_GDI support

This patch adds a new build flag ENABLE_FEAT_RME_GDI to enable this
feature, along with defining various related register fields. At this
point, when en

feat(cpufeat): introduce FEAT_RME_GDI support

This patch adds a new build flag ENABLE_FEAT_RME_GDI to enable this
feature, along with defining various related register fields. At this
point, when enabled, this feature enables the SA and NSP GPI encodings
by setting the corresponding bits in GPCCR_EL3.

Change-Id: I54152fbb3d19b176264e5d16acbcc866725dc290
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Timothy Hayes <timothy.hayes@arm.com>

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feat(cpufeat): add support for FEAT_RME_GPC2

This change adds support for FEAT_RME_GPC2 and Non-Secure-Only (NSO)
Physical Address Space.

Previously, all non-secure (NS) memory was accessible to th

feat(cpufeat): add support for FEAT_RME_GPC2

This change adds support for FEAT_RME_GPC2 and Non-Secure-Only (NSO)
Physical Address Space.

Previously, all non-secure (NS) memory was accessible to the secure
world and realm world. With GPC2 and the NSO bit in the GPT, memory
can now be restricted to the non-secure world only. This is enabled
automatically on supported systems when ENABLE_RME is true.

Change-Id: I9b70c3a23c5ec7d83bd787d0fb3edd55934f1d05
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Girish Pathak <girish.pathak@arm.com>

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fix(libc): fix coverity overflowed constant

Avoid overflow that may occur from math operations.

Coverity message:
-----------------
CID 457888: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)34.

fix(libc): fix coverity overflowed constant

Avoid overflow that may occur from math operations.

Coverity message:
-----------------
CID 457888: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)34.
overflow_const: Expression acc, where base is known to be equal to 16,
overflows the type of acc, which is type unsigned long long.

Change-Id: I41f22e22625a17826b2cedff101120918e23c8e8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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chore: ignore memory src pycache

Update the ignore entry to match the new tools/memory/src path

Change-Id: I3e356785afbbf8e14c16b5248a261bd65d164c28
Signed-off-by: Madhukar Pappireddy <madhukar.pap

chore: ignore memory src pycache

Update the ignore entry to match the new tools/memory/src path

Change-Id: I3e356785afbbf8e14c16b5248a261bd65d164c28
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(fvp): skip SP discovery through FFA_PARTITION_INFO_GET_REGS

The initialization function implemented for the dummy LSP of FVP port
invokes FFA_PARTITION_INFO_GET_REGS to obtain partition properti

fix(fvp): skip SP discovery through FFA_PARTITION_INFO_GET_REGS

The initialization function implemented for the dummy LSP of FVP port
invokes FFA_PARTITION_INFO_GET_REGS to obtain partition properties of
Secure Partitions managed by SPMC. This happens even before the normal
world is booted.

Hafnium SPMC mistakes this as a FF-A invocation from NWd. As per FF-A
version negotiation protocol, Hafnium locks the version of NWd to v1.3
whereas the NWd never got an opportunity to register its own framework
version.

This patch performs early exit from the helper utility to give NWd
endpoint/Hypervisor an opportunity to register its FF-A version with
SPM. We intentionally do not remove the helper utility as it will be
used in a different patchset for a new anticipated feature.

Change-Id: I54087bd2ad53355afeb024c0e4df6a5ba7ab125a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(scmi): fix coverity issue INTEGER_OVERFLOW

Use round_up_overflow to avoid any integer overflow from
protocol count.

Thsi fixes below coverity issue -

CID 457880: (#1 of 1): Overflowed constant

fix(scmi): fix coverity issue INTEGER_OVERFLOW

Use round_up_overflow to avoid any integer overflow from
protocol count.

Thsi fixes below coverity issue -

CID 457880: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)
4. overflow_const: Expression count - 1U, where count is known
to be equal to 0, underflows the type of count - 1U, which is
type unsigned int.

Change-Id: Ib55599fcb2a522e57271a6a07fb9bfd07e6953b9
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(libc): fix coverity overflowed constant

Assigning acc which of type unsigned long(long) with (L)LONG_MAX or (L)LONG_MIN
will cause a overflow of type acc.

Coverity Message:
-----------------
Ov

fix(libc): fix coverity overflowed constant

Assigning acc which of type unsigned long(long) with (L)LONG_MAX or (L)LONG_MIN
will cause a overflow of type acc.

Coverity Message:
-----------------
Overflowed constant (INTEGER_OVERFLOW)
overflow_const: Expression acc, where
neg ? -9223372036854775808L : 9223372036854775807L is known to be equal
to -9223372036854775808, underflows the type of acc, which is type
unsigned long.

Change-Id: Ic97c3ad8a2a281dfe7ef6b28b2500fd48e45f19e
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(psci): fix coverity issue with out-of-bounds read

Avoid OVERRUN on parent indices if accidental return negative value
from `get_pwr_lvl_state_idx`, so convert everything to use unsigned
int to a

fix(psci): fix coverity issue with out-of-bounds read

Avoid OVERRUN on parent indices if accidental return negative value
from `get_pwr_lvl_state_idx`, so convert everything to use unsigned
int to avoid Out-of-bounds read (OVERRUN)

Change-Id: Ie6d6fd34db9903e99b29e004fb46908aea8acd46
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(fvp): fix coverity issue unsigned_compare

Fixes less than zero comparison for unsigned value.

Issue Description:
CID 447712: (#1 of 1): Macro compares unsigned to 0 (NO_EFFECT)
unsigned_compare

fix(fvp): fix coverity issue unsigned_compare

Fixes less than zero comparison for unsigned value.

Issue Description:
CID 447712: (#1 of 1): Macro compares unsigned to 0 (NO_EFFECT)
unsigned_compare: This less-than-zero comparison of an
unsigned value is never true. power_level < 0ULL.

Change-Id: Ia06f8729ac78b05046402e29e30f55c5f0b9e215
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(gic): fix coverity issue INTEGER_OVERFLOW

Avoid unsigned underflow when spi_id_min is below the base.
Make all shifts in the CHIPR value composition 64-bit, to
avoid flagging overflow.

Change-I

fix(gic): fix coverity issue INTEGER_OVERFLOW

Avoid unsigned underflow when spi_id_min is below the base.
Make all shifts in the CHIPR value composition 64-bit, to
avoid flagging overflow.

Change-Id: I376809fc110ff45dd0682b4bcf8dab43cf03d300
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(scmi): fix coverity issue INTEGER_OVERFLOW

Fixes the following coverity issue -

CID 457917: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)
overflow_const: Expression lvl - 1U, where lvl is k

fix(scmi): fix coverity issue INTEGER_OVERFLOW

Fixes the following coverity issue -

CID 457917: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)
overflow_const: Expression lvl - 1U, where lvl is known to be equal
to 0, underflows the type of lvl - 1U, which is type unsigned int.

Change-Id: Id965c4b95159793944b3ef4658fd92e881d53c59
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "upstream_integrate_ddr_fw" into integration

* changes:
feat(s32g274ardb): add custom DDR FW UUID entry
fix(fiptool): skip Layerscape makefile for S32 build

feat(lfa): introduce support for call_again for LFA_PRIME

LFA_PRIME is a single-threaded operation that is not pinned to
a specific CPU. The implementation must support calls being
issued from diffe

feat(lfa): introduce support for call_again for LFA_PRIME

LFA_PRIME is a single-threaded operation that is not pinned to
a specific CPU. The implementation must support calls being
issued from different CPUs, even for several calls to prime the
same component.

This patch checks if the plat_lfa_load_auth_image return -EAGAIN
indicating that the platform expects the LFA_PRIME call to be
issued again. This is done by returning LFA_SUCCESS and setting
flags[0] to 1, indicating that LFA_PRIME is incomplete and must
be called again.

Change-Id: Ia3046b5467c50c4c51392bac3fb9e9533f2438db
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge "fix(tsp): add missing include" into integration

fix(tsp): add missing include

Depending on include order, u_register_t may be unknown in the file
platform_tsp.h. Include stdint.h to correct that.

Change-Id: I7aeb1d389048189e8ba1b5a48173d139dc29c

fix(tsp): add missing include

Depending on include order, u_register_t may be unknown in the file
platform_tsp.h. Include stdint.h to correct that.

Change-Id: I7aeb1d389048189e8ba1b5a48173d139dc29c0da
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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