1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_pro.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Pro must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Pro supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Pro needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_pro 30 31 /* ----------------------------------------------------------- 32 * CVE-2024-7881 is mitigated for C1-Pro using erratum 3684268 33 * workaround by disabling the affected prefetcher 34 * via IMP_CPUECTLR_EL1[49]. 35 * ----------------------------------------------------------- 36 */ 37workaround_reset_start c1_pro, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 38 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(49) 39 dsb sy 40workaround_reset_end c1_pro, CVE(2024, 7881) 41 42check_erratum_ls c1_pro, CVE(2024, 7881), CPU_REV(1, 0) 43 44workaround_reset_start c1_pro, ERRATUM(3362007), ERRATA_C1PRO_3362007 45 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(27) 46workaround_reset_end c1_pro, ERRATUM(3362007) 47 48check_erratum_ls c1_pro, ERRATUM(3362007), CPU_REV(0, 0) 49 50workaround_reset_start c1_pro, ERRATUM(3684268), ERRATA_C1PRO_3684268 51 sysreg_bit_set C1_PRO_IMP_CPUECTLR2_EL1, BIT(49) 52 dsb sy 53workaround_reset_end c1_pro, ERRATUM(3684268) 54 55check_erratum_ls c1_pro, ERRATUM(3684268), CPU_REV(1, 0) 56 57workaround_reset_start c1_pro, ERRATUM(3694158), ERRATA_C1PRO_3694158 58 mov x0, #5 59 msr C1_PRO_IMP_CPUPSELR_EL3, x0 60 isb 61 ldr x0, =0xd503329f 62 msr C1_PRO_IMP_CPUPOR_EL3, x0 63 ldr x0, =0xfffff3ff 64 msr C1_PRO_IMP_CPUPMR_EL3, x0 65 mov x1, #0 66 orr x1, x1, #1<<0 67 orr x1, x1, #3<<4 68 orr x1, x1, #0xf<<6 69 orr x1, x1, #1<<22 70 orr x1, x1, #1<<32 71 msr C1_PRO_IMP_CPUPCR_EL3, x1 72workaround_reset_end c1_pro, ERRATUM(3694158) 73 74check_erratum_ls c1_pro, ERRATUM(3694158), CPU_REV(1, 1) 75 76workaround_reset_start c1_pro, ERRATUM(3706576), ERRATA_C1PRO_3706576 77 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(37) 78workaround_reset_end c1_pro, ERRATUM(3706576) 79 80check_erratum_ls c1_pro, ERRATUM(3706576), CPU_REV(1, 0) 81 82cpu_reset_func_start c1_pro 83 /* ---------------------------------------------------- 84 * Disable speculative loads 85 * ---------------------------------------------------- 86 */ 87 msr SSBS, xzr 88 /* model bug: not cleared on reset */ 89 sysreg_bit_clear C1_PRO_IMP_CPUPWRCTLR_EL1, \ 90 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 91 enable_mpmm 92cpu_reset_func_end c1_pro 93 94 /* ---------------------------------------------------- 95 * HW will do the cache maintenance while powering down 96 * ---------------------------------------------------- 97 */ 98func c1_pro_core_pwr_dwn 99 /* --------------------------------------------------- 100 * Flip CPU power down bit in power control register. 101 * It will be set on powerdown and cleared on wakeup 102 * --------------------------------------------------- 103 */ 104 sysreg_bit_toggle C1_PRO_IMP_CPUPWRCTLR_EL1, \ 105 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 106 isb 107 signal_pabandon_handled 108 ret 109endfunc c1_pro_core_pwr_dwn 110 111 /* --------------------------------------------- 112 * This function provides Arm C1-Pro specific 113 * register information for crash reporting. 114 * It needs to return with x6 pointing to 115 * a list of register names in ascii and 116 * x8 - x15 having values of registers to be 117 * reported. 118 * --------------------------------------------- 119 */ 120.section .rodata.c1_pro_regs, "aS" 121c1_pro_regs: /* The ASCII list of register names to be reported */ 122 .asciz "imp_cpuectlr_el1", "" 123 124func c1_pro_cpu_reg_dump 125 adr x6, c1_pro_regs 126 mrs x8, C1_PRO_IMP_CPUECTLR_EL1 127 ret 128endfunc c1_pro_cpu_reg_dump 129 130declare_cpu_ops c1_pro, C1_PRO_MIDR, \ 131 c1_pro_reset_func, \ 132 c1_pro_core_pwr_dwn 133