1 /* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NEOVERSE_V3_H 8 #define NEOVERSE_V3_H 9 10 11 #define NEOVERSE_V3_VNAE_MIDR U(0x410FD830) 12 #define NEOVERSE_V3_MIDR U(0x410FD840) 13 14 /******************************************************************************* 15 * CPU Extended Control register specific definitions. 16 ******************************************************************************/ 17 #define NEOVERSE_V3_CPUECTLR_EL1 S3_0_C15_C1_4 18 19 /******************************************************************************* 20 * CPU Power Control register specific definitions 21 ******************************************************************************/ 22 #define NEOVERSE_V3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 23 #define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 24 25 /******************************************************************************* 26 * CPU Auxiliary control register 6 specific definitions 27 ******************************************************************************/ 28 #define NEOVERSE_V3_CPUACTLR6_EL1 S3_0_C15_C8_1 29 30 /******************************************************************************* 31 * CPU instruction patching register definitions 32 ******************************************************************************/ 33 #define NEOVERSE_V3_CPUPSELR_EL3 S3_6_C15_C8_0 34 #define NEOVERSE_V3_CPUPCR_EL3 S3_6_C15_C8_1 35 #define NEOVERSE_V3_CPUPOR_EL3 S3_6_C15_C8_2 36 #define NEOVERSE_V3_CPUPMR_EL3 S3_6_C15_C8_3 37 38 #ifndef __ASSEMBLER__ 39 long check_erratum_neoverse_v3_3701767(long cpu_rev); 40 #endif /* __ASSEMBLER__ */ 41 42 #endif /* NEOVERSE_V3_H */ 43