Merge "fix(rcar5): prevent boot CPU hot unplug" into integration

Merge "feat(rcar): rewrite console_renesas_register() in C" into integration

Merge changes from topics "qemu-sve", "xl/simd-hash" into integration

* changes:
feat(qemu): disable fpregs traps for QEMU in BL31
feat(crypto): enable the runtime instrumentation for crypto ext

Merge changes from topics "qemu-sve", "xl/simd-hash" into integration

* changes:
feat(qemu): disable fpregs traps for QEMU in BL31
feat(crypto): enable the runtime instrumentation for crypto extension
feat(crypto): enable access to SIMD crypto in BL1 and BL2
feat(crypto): enable floating point register traps in EL3
feat(crypto): build flag for SIMD crypto extensions for v8+ platform
refactor(build): add a default filter list for lib cflags

show more ...

Merge "fix(cpus): workaround for Cortex-A65AE erratum 1638571" into integration

Merge "feat(build): add HOSTLDFLAGS to pass flags to host links" into integration

Merge "feat(s32g274ardb): use DDR reset deassertion" into integration

Merge changes from topic "xlnx_fix_misra_common_fdt_split" into integration

* changes:
fix(libfdt): resolve misra 10.3 violations
feat(lib): use C/assembler for HI/LO macros
fix(libfdt): addin

Merge changes from topic "xlnx_fix_misra_common_fdt_split" into integration

* changes:
fix(libfdt): resolve misra 10.3 violations
feat(lib): use C/assembler for HI/LO macros
fix(libfdt): adding missing curly braces
fix(libfdt): fix misra 14.4 and 15.6 violations
fix(libfdt): typecast operands to match data type

show more ...

feat(qemu): disable fpregs traps for QEMU in BL31

The BL31 boot process of QEMU requires, as a workaround, disabling of
fpregs trap in BL31. The fpregs trap is by default enabled and therefore
it ne

feat(qemu): disable fpregs traps for QEMU in BL31

The BL31 boot process of QEMU requires, as a workaround, disabling of
fpregs trap in BL31. The fpregs trap is by default enabled and therefore
it needed to be explicitly disabled for the BL31 setup for QEMU.

Change-Id: Id958e5e72a1fae81553ba320dcdb232bc705b835
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

fix(cpus): workaround for Cortex-A65AE erratum 1638571

Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A65AE erratum 1638571

Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.

This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1344564/latest

Change-Id: I861230de94a105fd52f9c8ef7e7551a2633c065b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

Merge "feat(rcar): test only for SCIF TX FIFO empty before writing the FIFO" into integration

feat(crypto): enable the runtime instrumentation for crypto extension

Add runtime instrumentation for the authentication process in BL1
and BL2, to measure the speedup of the authentication after
en

feat(crypto): enable the runtime instrumentation for crypto extension

Add runtime instrumentation for the authentication process in BL1
and BL2, to measure the speedup of the authentication after
enabling the crypto extension.

Change-Id: Ieea927e7e8bd0d109525f28b06510acf0ab62e5c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

feat(crypto): enable access to SIMD crypto in BL1 and BL2

Disable the floating point register traps in image auth and
loading in BL1 and BL2 to allow the access to SIMD crypto
extension during the b

feat(crypto): enable access to SIMD crypto in BL1 and BL2

Disable the floating point register traps in image auth and
loading in BL1 and BL2 to allow the access to SIMD crypto
extension during the booting process.

Change-Id: I9c20715d54f5d2988aa706e91e1a657dcd06dfc2
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

feat(crypto): enable floating point register traps in EL3

To prevent the leakage of EL3 information to lower ELs, access to
floating point registers needed to be traped to EL3 unless necessary
(e.g

feat(crypto): enable floating point register traps in EL3

To prevent the leakage of EL3 information to lower ELs, access to
floating point registers needed to be traped to EL3 unless necessary
(e.g the SIMD crypto extension, SIMD context save/restore).

Change-Id: I28a734c43d3e965de87ccc08e99f86669729871f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

feat(crypto): build flag for SIMD crypto extensions for v8+ platform

Add new build flags ENABLE_FEAT_CRYPTO to enable SIMD crypto extension
for hash256 in bootflow authentication process and ENABLE_

feat(crypto): build flag for SIMD crypto extensions for v8+ platform

Add new build flags ENABLE_FEAT_CRYPTO to enable SIMD crypto extension
for hash256 in bootflow authentication process and ENABLE_FEAT_CRYPTO_SHA3
to enable SIMD crypto extension for sha384 and sha512 in bootflow authentication
process for Arm platform greater than v8.0.

Change-Id: I6e52feb318136910d34cafd89319bf94f90e16fc
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

refactor(build): add a default filter list for lib cflags

All libraries use the same set of cflags during compilation,
because the build macro `MAKE_C_LIB` for libraries is hard-coded
to use the com

refactor(build): add a default filter list for lib cflags

All libraries use the same set of cflags during compilation,
because the build macro `MAKE_C_LIB` for libraries is hard-coded
to use the common cflags variable `TF_CFLAGS` along with
library-specific `LIB_CFLAGS` in the make command.
However for SIMD crypto extension, some cflags have to
be removed from the build. So add an optional argument
of a list of cflags that needed to be filtered out
for a particular library, to allow more flexibility in the
choice of cflags during compilation.

Change-Id: I53f6f3c6efa28ed4fa2d451270f10f448de2af97
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

Merge changes from topic "ar/smccc_arch_wa_4" into integration

* changes:
fix(cpus): remove C1-Premium erratum 3651221
fix(cpus): remove C1-Ultra erratum 3651221
fix(cpus): correct CVE-2024-78

Merge changes from topic "ar/smccc_arch_wa_4" into integration

* changes:
fix(cpus): remove C1-Premium erratum 3651221
fix(cpus): remove C1-Ultra erratum 3651221
fix(cpus): correct CVE-2024-7881 workaround and drop duplicate erratum

show more ...

fix(cpus): remove C1-Premium erratum 3651221

This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Premium erratum 3651221 [2] support.

fix(cpus): remove C1-Premium erratum 3651221

This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Premium erratum 3651221 [2] support.

[1] : https://developer.arm.com/documentation/110326/latest/
[2] : https://developer.arm.com/documentation/111078/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I40b37ec62788884ae5c0a0bb3eb4b924622ffe55

show more ...

fix(cpus): remove C1-Ultra erratum 3651221

This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Ultra erratum 3651221 [2] support.

[1]

fix(cpus): remove C1-Ultra erratum 3651221

This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Ultra erratum 3651221 [2] support.

[1] : https://developer.arm.com/documentation/110326/latest/
[2] : https://developer.arm.com/documentation/111077/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If7ea433e4614f92333e788e3f6b366db22c92f0d

show more ...

fix(cpus): correct CVE-2024-7881 workaround and drop duplicate erratum

Fix the CVE-2024-7881 [1] workaround for C1-Pro. The previously
implemented erratum 3684268 [2] programmed the same control bit

fix(cpus): correct CVE-2024-7881 workaround and drop duplicate erratum

Fix the CVE-2024-7881 [1] workaround for C1-Pro. The previously
implemented erratum 3684268 [2] programmed the same control bit and
overlapped functionally with the CVE workaround, so the duplicate
erratum is removed.

Reference:
[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/SDEN-3273080/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6207c49486e4020f34c862ad40ec3137bd3684cc

show more ...

Merge changes I8d332dbe,I9d30b6f9,I2fd7eece,Ibcd65f39,I86cc5e97 into integration

* changes:
feat(bl2): support RESET_TO_BL2 and ENABLE_RME
fix(build): fix BL2_CPPFLAGS when ENABLE_RME is set
f

Merge changes I8d332dbe,I9d30b6f9,I2fd7eece,Ibcd65f39,I86cc5e97 into integration

* changes:
feat(bl2): support RESET_TO_BL2 and ENABLE_RME
fix(build): fix BL2_CPPFLAGS when ENABLE_RME is set
fix(fvp): increase resident text size of BL2
fix(arm): support FCONF when TRANSFER_LIST and RESET_BL2 is set
fix(arm): update next image's ep info with the FW config address

show more ...

feat(bl2): support RESET_TO_BL2 and ENABLE_RME

When RSE is used as the root of trust along with CPU that supports RME
there is a need to enable both RESET_TO_BL2 and ENABLE_RME.

In current bl2_main

feat(bl2): support RESET_TO_BL2 and ENABLE_RME

When RSE is used as the root of trust along with CPU that supports RME
there is a need to enable both RESET_TO_BL2 and ENABLE_RME.

In current bl2_main there are two different code paths for RESET_BL2,
one handles BL2 running in EL1 and other for BL2 running in EL3.

When RME is enabled, BL2 always runs at EL3 but the current flow calls
bl2_early_platform_setup2, bl2_plat_arch_setup instead of
bl2_el3_early_platform_setup, bl2_el3_plat_arch_setup. Adding RME,
TRANSFER_LIST, ROMLIB support in bl2_el3_* helpers makes
arm_bl2_el3_setup.c almost identical to arm_bl2_setup.c.

This patch removes bl2_el3_plat helpers and related files. Now different
combinations of RESET_TO_BL2, ENABLE_RME are handled in common bl2_setup
routines in arm_bl2_setup.c. This helps to have common place to support
new features and build flags for BL2 irrespective of which EL the BL2
runs.

BREAKING-CHANGE: This patch also changes all existing platform files and
functions that use format bl2_el3_* to bl2_plat helpers. If any platform
or out-of-tree platforms that need to support running BL2 in EL1 or EL3
must now handle it in bl2_early_platform_setup2 and bl2_plat_arch_setup.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I8d332dbe2de1db3b69319496c8d04626cdcf4140

show more ...

fix(build): fix BL2_CPPFLAGS when ENABLE_RME is set

Add IMAGE_AT_EL3 to BL2_CPPFLAGS as BL2 runs at EL3 when ENABLE_RME is
set. And use IMAGE_AT_EL3 for misc_helpers.S that is common for all BLs.

T

fix(build): fix BL2_CPPFLAGS when ENABLE_RME is set

Add IMAGE_AT_EL3 to BL2_CPPFLAGS as BL2 runs at EL3 when ENABLE_RME is
set. And use IMAGE_AT_EL3 for misc_helpers.S that is common for all BLs.

This fix enables cpu_reset ops in CPU libs when RME is enabled.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I9d30b6f900a5fed1993b1c09156830290203ed33

show more ...

fix(fvp): increase resident text size of BL2

Enabling new CPU library code like Venom requires to set build flags
HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0. When build along with
RESET_TO_BL=1 (BL2

fix(fvp): increase resident text size of BL2

Enabling new CPU library code like Venom requires to set build flags
HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0. When build along with
RESET_TO_BL=1 (BL2 in EL3 case) causes increase in resident text size
of BL2.

This is applicable in case of PLAT=fvp as it includes a lot of CPU_LIBS
and might not be the case of other platforms as it includes only
specific CPU libs.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I2fd7eecebd9a2bdcbdc9fbbf4cecc2d659740931

show more ...

Merge "fix(drtm): map DLME and DRTM parameter region as execute-never" into integration

Merge "chore: bump event log library" into integration