| e9044480 | 13-Sep-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194
This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, wa
Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194
This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, was
incorrect.
Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 029dd14e | 06-Jul-2018 |
Jeetesh Burman <jburman@nvidia.com> |
Tegra194: add SE support to generate SHA256 of TZRAM
The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This
memory loses power when we enter System Suspend and so its contents are
s
Tegra194: add SE support to generate SHA256 of TZRAM
The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.
This patch adds driver for the SE engine, with APIs to calculate the hash
and store to PMC scratch registers.
Change-Id: I04cc0eb7f54c69d64b6c34fc2ff62e4cfbdd43b2
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
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| ceb12020 | 23-Jan-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: organize the memory/mmio map to make it linear
This patch organizes the platform memory/mmio map, so that the base
addresses for the apertures line up in ascending order. This makes
it eas
Tegra194: organize the memory/mmio map to make it linear
This patch organizes the platform memory/mmio map, so that the base
addresses for the apertures line up in ascending order. This makes
it easier for the xlat_tables_v2 library to create mappings for each
mmap_add_region call.
Change-Id: Ie1938ba043820625c9fea904009a3d2ccd29f7b3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 33a8ba6a | 09-Feb-2018 |
Steven Kao <skao@nvidia.com> |
Tegra194: support for boot params wider than 32-bits
The previous bootloader is not able to pass boot params wider than
32-bits due to an oversight in the scratch register being used. A
new secure s
Tegra194: support for boot params wider than 32-bits
The previous bootloader is not able to pass boot params wider than
32-bits due to an oversight in the scratch register being used. A
new secure scratch register #75 has been assigned to pass the higher
bits.
This patch adds support to parse the higher bits from scratch #75
and use them in calculating the base address for the location of
the boot params.
Scratch #75 format
====================
31:16 - bl31_plat_params high address
15:0 - bl31_params high address
Change-Id: Id53c45f70a9cb370c776ed7c82ad3f2258576a80
Signed-off-by: Steven Kao <skao@nvidia.com>
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| 34a6610a | 07-Mar-2018 |
Puneet Saxena <puneets@nvidia.com> |
Tegra194: memctrl: set reorder depth limit for PCIE blocks
HW bug in third party PCIE IP - PCIE datapath hangs when there are
more than 28 outstanding requests on data backbone for x1 controller.
S
Tegra194: memctrl: set reorder depth limit for PCIE blocks
HW bug in third party PCIE IP - PCIE datapath hangs when there are
more than 28 outstanding requests on data backbone for x1 controller.
Suggested SW WAR is to limit reorder_depth_limit to 16 for
PCIE 1W/2AW/3W clients.
Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
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| 1296da6d | 05-Jan-2018 |
Puneet Saxena <puneets@nvidia.com> |
Tegra194: memctrl: update mss reprogramming as HW PROD settings
Memory clients are divided in to ISO/NonISO/Order/Unordered/Low
BW/High BW. Based on the client types, HW team recommends, different
m
Tegra194: memctrl: update mss reprogramming as HW PROD settings
Memory clients are divided in to ISO/NonISO/Order/Unordered/Low
BW/High BW. Based on the client types, HW team recommends, different
memory ordering settings, IO coherency settings and SMMU register settings
for optimized performance of the MC clients.
For example ordered ISO clients should be set as strongly ordered and
should bypass SCF and directly access MC hence set as
FORCE_NON_COHERENT. Like this there are multiple recommendations
for all of the MC clients.
This change sets all these MC registers as per HW spec file.
Change-Id: I8a8a0887cd86bf6fe8ac7835df6c888855738cd9
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 221b8e57 | 23-Dec-2017 |
Krishna Reddy <vdumpa@nvidia.com> |
Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent
Force memory transactions from viw and viflar/w as non-coherent from
no-override. This is necessary as iso clients shouldn't us
Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent
Force memory transactions from viw and viflar/w as non-coherent from
no-override. This is necessary as iso clients shouldn't use coherent
path and stage-2 smmu mappings won't mark transactions as non-coherent.
For native case, no-override works. But, not for virtualization case.
Change-Id: I1a8fc17787c8d0f8579bdaeeb719084993e27276
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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| 95f68bc4 | 18-Dec-2017 |
Krishna Reddy <vdumpa@nvidia.com> |
Tegra194: memctrl: fix bug in client order id reg value generation
Client order id reset values are incorrectly and'ed with
mc_client_order_id macro, which resulted in getting reg value as
always ze
Tegra194: memctrl: fix bug in client order id reg value generation
Client order id reset values are incorrectly and'ed with
mc_client_order_id macro, which resulted in getting reg value as
always zero. Updated mc_client_order_id macro to avoid and'ing outside
the macro, to take the reg value and update specific bit field
as necessary.
Change-Id: I880be6e4291d7cd58cf70d7c247a4044e57edd9e
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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| c766adce | 19-Dec-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: memctrl: enable mc coalescer
This patch enable the Memory Controller's "Coalescer" feature to
improve performance of memory transactions.
Change-Id: I50ba0354116284f85d9e170c293ce77e9f3fb
Tegra194: memctrl: enable mc coalescer
This patch enable the Memory Controller's "Coalescer" feature to
improve performance of memory transactions.
Change-Id: I50ba0354116284f85d9e170c293ce77e9f3fb4d8
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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