1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp_shres_helpers.h> 26 #include <stm32mp1_dbgmcu.h> 27 #include <stm32mp1_private.h> 28 #endif 29 30 /******************************************************************************* 31 * CHIP ID 32 ******************************************************************************/ 33 #define STM32MP157C_PART_NB U(0x05000000) 34 #define STM32MP157A_PART_NB U(0x05000001) 35 #define STM32MP153C_PART_NB U(0x05000024) 36 #define STM32MP153A_PART_NB U(0x05000025) 37 #define STM32MP151C_PART_NB U(0x0500002E) 38 #define STM32MP151A_PART_NB U(0x0500002F) 39 40 #define STM32MP1_REV_B U(0x2000) 41 42 /******************************************************************************* 43 * PACKAGE ID 44 ******************************************************************************/ 45 #define PKG_AA_LFBGA448 U(4) 46 #define PKG_AB_LFBGA354 U(3) 47 #define PKG_AC_TFBGA361 U(2) 48 #define PKG_AD_TFBGA257 U(1) 49 50 /******************************************************************************* 51 * STM32MP1 memory map related constants 52 ******************************************************************************/ 53 #define STM32MP_ROM_BASE U(0x00000000) 54 #define STM32MP_ROM_SIZE U(0x00020000) 55 56 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 57 #define STM32MP_SYSRAM_SIZE U(0x00040000) 58 59 /* DDR configuration */ 60 #define STM32MP_DDR_BASE U(0xC0000000) 61 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 62 #ifdef AARCH32_SP_OPTEE 63 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 64 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 65 #else 66 #define STM32MP_DDR_S_SIZE U(0) 67 #define STM32MP_DDR_SHMEM_SIZE U(0) 68 #endif 69 70 /* DDR power initializations */ 71 #ifndef __ASSEMBLER__ 72 enum ddr_type { 73 STM32MP_DDR3, 74 STM32MP_LPDDR2, 75 STM32MP_LPDDR3 76 }; 77 #endif 78 79 /* Section used inside TF binaries */ 80 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 81 /* 256 Octets reserved for header */ 82 #define STM32MP_HEADER_SIZE U(0x00000100) 83 84 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 85 STM32MP_PARAM_LOAD_SIZE + \ 86 STM32MP_HEADER_SIZE) 87 88 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 89 (STM32MP_PARAM_LOAD_SIZE + \ 90 STM32MP_HEADER_SIZE)) 91 92 #ifdef AARCH32_SP_OPTEE 93 #define STM32MP_BL32_SIZE U(0) 94 95 #define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE 96 97 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ 98 STM32MP_OPTEE_BASE) 99 #else 100 #if STACK_PROTECTOR_ENABLED 101 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */ 102 #else 103 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 KB for BL32 */ 104 #endif 105 #endif 106 107 #define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \ 108 STM32MP_SYSRAM_SIZE - \ 109 STM32MP_BL32_SIZE) 110 111 #ifdef AARCH32_SP_OPTEE 112 #if STACK_PROTECTOR_ENABLED 113 #define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */ 114 #else 115 #define STM32MP_BL2_SIZE U(0x00018000) /* 92 KB for BL2 */ 116 #endif 117 #else 118 #if STACK_PROTECTOR_ENABLED 119 #define STM32MP_BL2_SIZE U(0x00019000) /* 96 KB for BL2 */ 120 #else 121 #define STM32MP_BL2_SIZE U(0x00017000) /* 88 KB for BL2 */ 122 #endif 123 #endif 124 125 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 126 STM32MP_BL2_SIZE) 127 128 /* BL2 and BL32/sp_min require 4 tables */ 129 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 130 131 /* 132 * MAX_MMAP_REGIONS is usually: 133 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 134 */ 135 #if defined(IMAGE_BL2) 136 #define MAX_MMAP_REGIONS 11 137 #endif 138 #if defined(IMAGE_BL32) 139 #define MAX_MMAP_REGIONS 6 140 #endif 141 142 /* DTB initialization value */ 143 #define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 144 145 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 146 STM32MP_DTB_SIZE) 147 148 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 149 150 /* Define maximum page size for NAND devices */ 151 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 152 153 /******************************************************************************* 154 * STM32MP1 RAW partition offset for MTD devices 155 ******************************************************************************/ 156 #define STM32MP_NOR_BL33_OFFSET U(0x00080000) 157 #ifdef AARCH32_SP_OPTEE 158 #define STM32MP_NOR_TEEH_OFFSET U(0x00280000) 159 #define STM32MP_NOR_TEED_OFFSET U(0x002C0000) 160 #define STM32MP_NOR_TEEX_OFFSET U(0x00300000) 161 #endif 162 163 #define STM32MP_NAND_BL33_OFFSET U(0x00200000) 164 #ifdef AARCH32_SP_OPTEE 165 #define STM32MP_NAND_TEEH_OFFSET U(0x00600000) 166 #define STM32MP_NAND_TEED_OFFSET U(0x00680000) 167 #define STM32MP_NAND_TEEX_OFFSET U(0x00700000) 168 #endif 169 170 /******************************************************************************* 171 * STM32MP1 device/io map related constants (used for MMU) 172 ******************************************************************************/ 173 #define STM32MP1_DEVICE1_BASE U(0x40000000) 174 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 175 176 #define STM32MP1_DEVICE2_BASE U(0x80000000) 177 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 178 179 /******************************************************************************* 180 * STM32MP1 RCC 181 ******************************************************************************/ 182 #define RCC_BASE U(0x50000000) 183 184 /******************************************************************************* 185 * STM32MP1 PWR 186 ******************************************************************************/ 187 #define PWR_BASE U(0x50001000) 188 189 /******************************************************************************* 190 * STM32MP1 GPIO 191 ******************************************************************************/ 192 #define GPIOA_BASE U(0x50002000) 193 #define GPIOB_BASE U(0x50003000) 194 #define GPIOC_BASE U(0x50004000) 195 #define GPIOD_BASE U(0x50005000) 196 #define GPIOE_BASE U(0x50006000) 197 #define GPIOF_BASE U(0x50007000) 198 #define GPIOG_BASE U(0x50008000) 199 #define GPIOH_BASE U(0x50009000) 200 #define GPIOI_BASE U(0x5000A000) 201 #define GPIOJ_BASE U(0x5000B000) 202 #define GPIOK_BASE U(0x5000C000) 203 #define GPIOZ_BASE U(0x54004000) 204 #define GPIO_BANK_OFFSET U(0x1000) 205 206 /* Bank IDs used in GPIO driver API */ 207 #define GPIO_BANK_A U(0) 208 #define GPIO_BANK_B U(1) 209 #define GPIO_BANK_C U(2) 210 #define GPIO_BANK_D U(3) 211 #define GPIO_BANK_E U(4) 212 #define GPIO_BANK_F U(5) 213 #define GPIO_BANK_G U(6) 214 #define GPIO_BANK_H U(7) 215 #define GPIO_BANK_I U(8) 216 #define GPIO_BANK_J U(9) 217 #define GPIO_BANK_K U(10) 218 #define GPIO_BANK_Z U(25) 219 220 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 221 222 /******************************************************************************* 223 * STM32MP1 UART 224 ******************************************************************************/ 225 #define USART1_BASE U(0x5C000000) 226 #define USART2_BASE U(0x4000E000) 227 #define USART3_BASE U(0x4000F000) 228 #define UART4_BASE U(0x40010000) 229 #define UART5_BASE U(0x40011000) 230 #define USART6_BASE U(0x44003000) 231 #define UART7_BASE U(0x40018000) 232 #define UART8_BASE U(0x40019000) 233 #define STM32MP_UART_BAUDRATE U(115200) 234 235 /* For UART crash console */ 236 #define STM32MP_DEBUG_USART_BASE UART4_BASE 237 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 238 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 239 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 240 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 241 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 242 #define DEBUG_UART_TX_GPIO_PORT 11 243 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 244 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 245 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 246 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 247 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 248 249 /******************************************************************************* 250 * STM32MP1 ETZPC 251 ******************************************************************************/ 252 #define STM32MP1_ETZPC_BASE U(0x5C007000) 253 254 /* ETZPC TZMA IDs */ 255 #define STM32MP1_ETZPC_TZMA_ROM U(0) 256 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 257 258 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 259 260 /* ETZPC DECPROT IDs */ 261 #define STM32MP1_ETZPC_STGENC_ID 0 262 #define STM32MP1_ETZPC_BKPSRAM_ID 1 263 #define STM32MP1_ETZPC_IWDG1_ID 2 264 #define STM32MP1_ETZPC_USART1_ID 3 265 #define STM32MP1_ETZPC_SPI6_ID 4 266 #define STM32MP1_ETZPC_I2C4_ID 5 267 #define STM32MP1_ETZPC_RNG1_ID 7 268 #define STM32MP1_ETZPC_HASH1_ID 8 269 #define STM32MP1_ETZPC_CRYP1_ID 9 270 #define STM32MP1_ETZPC_DDRCTRL_ID 10 271 #define STM32MP1_ETZPC_DDRPHYC_ID 11 272 #define STM32MP1_ETZPC_I2C6_ID 12 273 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 274 275 #define STM32MP1_ETZPC_TIM2_ID 16 276 #define STM32MP1_ETZPC_TIM3_ID 17 277 #define STM32MP1_ETZPC_TIM4_ID 18 278 #define STM32MP1_ETZPC_TIM5_ID 19 279 #define STM32MP1_ETZPC_TIM6_ID 20 280 #define STM32MP1_ETZPC_TIM7_ID 21 281 #define STM32MP1_ETZPC_TIM12_ID 22 282 #define STM32MP1_ETZPC_TIM13_ID 23 283 #define STM32MP1_ETZPC_TIM14_ID 24 284 #define STM32MP1_ETZPC_LPTIM1_ID 25 285 #define STM32MP1_ETZPC_WWDG1_ID 26 286 #define STM32MP1_ETZPC_SPI2_ID 27 287 #define STM32MP1_ETZPC_SPI3_ID 28 288 #define STM32MP1_ETZPC_SPDIFRX_ID 29 289 #define STM32MP1_ETZPC_USART2_ID 30 290 #define STM32MP1_ETZPC_USART3_ID 31 291 #define STM32MP1_ETZPC_UART4_ID 32 292 #define STM32MP1_ETZPC_UART5_ID 33 293 #define STM32MP1_ETZPC_I2C1_ID 34 294 #define STM32MP1_ETZPC_I2C2_ID 35 295 #define STM32MP1_ETZPC_I2C3_ID 36 296 #define STM32MP1_ETZPC_I2C5_ID 37 297 #define STM32MP1_ETZPC_CEC_ID 38 298 #define STM32MP1_ETZPC_DAC_ID 39 299 #define STM32MP1_ETZPC_UART7_ID 40 300 #define STM32MP1_ETZPC_UART8_ID 41 301 #define STM32MP1_ETZPC_MDIOS_ID 44 302 #define STM32MP1_ETZPC_TIM1_ID 48 303 #define STM32MP1_ETZPC_TIM8_ID 49 304 #define STM32MP1_ETZPC_USART6_ID 51 305 #define STM32MP1_ETZPC_SPI1_ID 52 306 #define STM32MP1_ETZPC_SPI4_ID 53 307 #define STM32MP1_ETZPC_TIM15_ID 54 308 #define STM32MP1_ETZPC_TIM16_ID 55 309 #define STM32MP1_ETZPC_TIM17_ID 56 310 #define STM32MP1_ETZPC_SPI5_ID 57 311 #define STM32MP1_ETZPC_SAI1_ID 58 312 #define STM32MP1_ETZPC_SAI2_ID 59 313 #define STM32MP1_ETZPC_SAI3_ID 60 314 #define STM32MP1_ETZPC_DFSDM_ID 61 315 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 316 #define STM32MP1_ETZPC_LPTIM2_ID 64 317 #define STM32MP1_ETZPC_LPTIM3_ID 65 318 #define STM32MP1_ETZPC_LPTIM4_ID 66 319 #define STM32MP1_ETZPC_LPTIM5_ID 67 320 #define STM32MP1_ETZPC_SAI4_ID 68 321 #define STM32MP1_ETZPC_VREFBUF_ID 69 322 #define STM32MP1_ETZPC_DCMI_ID 70 323 #define STM32MP1_ETZPC_CRC2_ID 71 324 #define STM32MP1_ETZPC_ADC_ID 72 325 #define STM32MP1_ETZPC_HASH2_ID 73 326 #define STM32MP1_ETZPC_RNG2_ID 74 327 #define STM32MP1_ETZPC_CRYP2_ID 75 328 #define STM32MP1_ETZPC_SRAM1_ID 80 329 #define STM32MP1_ETZPC_SRAM2_ID 81 330 #define STM32MP1_ETZPC_SRAM3_ID 82 331 #define STM32MP1_ETZPC_SRAM4_ID 83 332 #define STM32MP1_ETZPC_RETRAM_ID 84 333 #define STM32MP1_ETZPC_OTG_ID 85 334 #define STM32MP1_ETZPC_SDMMC3_ID 86 335 #define STM32MP1_ETZPC_DLYBSD3_ID 87 336 #define STM32MP1_ETZPC_DMA1_ID 88 337 #define STM32MP1_ETZPC_DMA2_ID 89 338 #define STM32MP1_ETZPC_DMAMUX_ID 90 339 #define STM32MP1_ETZPC_FMC_ID 91 340 #define STM32MP1_ETZPC_QSPI_ID 92 341 #define STM32MP1_ETZPC_DLYBQ_ID 93 342 #define STM32MP1_ETZPC_ETH_ID 94 343 #define STM32MP1_ETZPC_RSV_ID 95 344 345 #define STM32MP_ETZPC_MAX_ID 96 346 347 /******************************************************************************* 348 * STM32MP1 TZC (TZ400) 349 ******************************************************************************/ 350 #define STM32MP1_TZC_BASE U(0x5C006000) 351 352 #define STM32MP1_TZC_A7_ID U(0) 353 #define STM32MP1_TZC_M4_ID U(1) 354 #define STM32MP1_TZC_LCD_ID U(3) 355 #define STM32MP1_TZC_GPU_ID U(4) 356 #define STM32MP1_TZC_MDMA_ID U(5) 357 #define STM32MP1_TZC_DMA_ID U(6) 358 #define STM32MP1_TZC_USB_HOST_ID U(7) 359 #define STM32MP1_TZC_USB_OTG_ID U(8) 360 #define STM32MP1_TZC_SDMMC_ID U(9) 361 #define STM32MP1_TZC_ETH_ID U(10) 362 #define STM32MP1_TZC_DAP_ID U(15) 363 364 #define STM32MP1_FILTER_BIT_ALL U(3) 365 366 /******************************************************************************* 367 * STM32MP1 SDMMC 368 ******************************************************************************/ 369 #define STM32MP_SDMMC1_BASE U(0x58005000) 370 #define STM32MP_SDMMC2_BASE U(0x58007000) 371 #define STM32MP_SDMMC3_BASE U(0x48004000) 372 373 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 374 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 375 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 376 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 377 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 378 379 /******************************************************************************* 380 * STM32MP1 BSEC / OTP 381 ******************************************************************************/ 382 #define STM32MP1_OTP_MAX_ID 0x5FU 383 #define STM32MP1_UPPER_OTP_START 0x20U 384 385 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 386 387 /* OTP offsets */ 388 #define DATA0_OTP U(0) 389 #define PART_NUMBER_OTP U(1) 390 #define NAND_OTP U(9) 391 #define PACKAGE_OTP U(16) 392 #define HW2_OTP U(18) 393 394 /* OTP mask */ 395 /* DATA0 */ 396 #define DATA0_OTP_SECURED BIT(6) 397 398 /* PART NUMBER */ 399 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 400 #define PART_NUMBER_OTP_PART_SHIFT 0 401 402 /* PACKAGE */ 403 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 404 #define PACKAGE_OTP_PKG_SHIFT 27 405 406 /* IWDG OTP */ 407 #define HW2_OTP_IWDG_HW_POS U(3) 408 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 409 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 410 411 /* HW2 OTP */ 412 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 413 414 /* NAND OTP */ 415 /* NAND parameter storage flag */ 416 #define NAND_PARAM_STORED_IN_OTP BIT(31) 417 418 /* NAND page size in bytes */ 419 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 420 #define NAND_PAGE_SIZE_SHIFT 29 421 #define NAND_PAGE_SIZE_2K U(0) 422 #define NAND_PAGE_SIZE_4K U(1) 423 #define NAND_PAGE_SIZE_8K U(2) 424 425 /* NAND block size in pages */ 426 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 427 #define NAND_BLOCK_SIZE_SHIFT 27 428 #define NAND_BLOCK_SIZE_64_PAGES U(0) 429 #define NAND_BLOCK_SIZE_128_PAGES U(1) 430 #define NAND_BLOCK_SIZE_256_PAGES U(2) 431 432 /* NAND number of block (in unit of 256 blocs) */ 433 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 434 #define NAND_BLOCK_NB_SHIFT 19 435 #define NAND_BLOCK_NB_UNIT U(256) 436 437 /* NAND bus width in bits */ 438 #define NAND_WIDTH_MASK BIT(18) 439 #define NAND_WIDTH_SHIFT 18 440 441 /* NAND number of ECC bits per 512 bytes */ 442 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 443 #define NAND_ECC_BIT_NB_SHIFT 15 444 #define NAND_ECC_BIT_NB_UNSET U(0) 445 #define NAND_ECC_BIT_NB_1_BITS U(1) 446 #define NAND_ECC_BIT_NB_4_BITS U(2) 447 #define NAND_ECC_BIT_NB_8_BITS U(3) 448 #define NAND_ECC_ON_DIE U(4) 449 450 /* NAND number of planes */ 451 #define NAND_PLANE_BIT_NB_MASK BIT(14) 452 453 /******************************************************************************* 454 * STM32MP1 TAMP 455 ******************************************************************************/ 456 #define TAMP_BASE U(0x5C00A000) 457 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 458 459 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 460 static inline uint32_t tamp_bkpr(uint32_t idx) 461 { 462 return TAMP_BKP_REGISTER_BASE + (idx << 2); 463 } 464 #endif 465 466 /******************************************************************************* 467 * STM32MP1 DDRCTRL 468 ******************************************************************************/ 469 #define DDRCTRL_BASE U(0x5A003000) 470 471 /******************************************************************************* 472 * STM32MP1 DDRPHYC 473 ******************************************************************************/ 474 #define DDRPHYC_BASE U(0x5A004000) 475 476 /******************************************************************************* 477 * STM32MP1 IWDG 478 ******************************************************************************/ 479 #define IWDG_MAX_INSTANCE U(2) 480 #define IWDG1_INST U(0) 481 #define IWDG2_INST U(1) 482 483 #define IWDG1_BASE U(0x5C003000) 484 #define IWDG2_BASE U(0x5A002000) 485 486 /******************************************************************************* 487 * STM32MP1 I2C4 488 ******************************************************************************/ 489 #define I2C4_BASE U(0x5C002000) 490 491 /******************************************************************************* 492 * STM32MP1 DBGMCU 493 ******************************************************************************/ 494 #define DBGMCU_BASE U(0x50081000) 495 496 /******************************************************************************* 497 * Device Tree defines 498 ******************************************************************************/ 499 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 500 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 501 #define DT_PWR_COMPAT "st,stm32mp1-pwr" 502 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 503 #define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" 504 505 #endif /* STM32MP1_DEF_H */ 506