| caa3e7e0 | 22-Apr-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
linker_script: move .data section to bl_common.ld.h
Move the data section to the common header.
I slightly tweaked some scripts as follows:
[1] bl1.ld.S has ALIGN(16). I added DATA_ALIGN macro, wh
linker_script: move .data section to bl_common.ld.h
Move the data section to the common header.
I slightly tweaked some scripts as follows:
[1] bl1.ld.S has ALIGN(16). I added DATA_ALIGN macro, which is 1
by default, but overridden by bl1.ld.S. Currently, ALIGN(16)
of the .data section is redundant because commit 412865907699
("Fix boot failures on some builds linked with ld.lld.") padded
out the previous section to work around the issue of LLD version
<= 10.0. This will be fixed in the future release of LLVM, so
I am keeping the proper way to align LMA.
[2] bl1.ld.S and bl2_el3.ld.S define __DATA_RAM_{START,END}__ instead
of __DATA_{START,END}__. I put them out of the .data section.
[3] SORT_BY_ALIGNMENT() is missing tsp.ld.S, sp_min.ld.S, and
mediatek/mt6795/bl31.ld.S. This commit adds SORT_BY_ALIGNMENT()
for all images, so the symbol order in those three will change,
but I do not think it is a big deal.
Change-Id: I215bb23c319f045cd88e6f4e8ee2518c67f03692
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| a7739bc7 | 26-Mar-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
linker_script: move bss section to bl_common.ld.h
Move the bss section to the common header. This adds BAKERY_LOCK_NORMAL
and PMF_TIMESTAMP, which previously existed only in BL31. This is not
a big
linker_script: move bss section to bl_common.ld.h
Move the bss section to the common header. This adds BAKERY_LOCK_NORMAL
and PMF_TIMESTAMP, which previously existed only in BL31. This is not
a big deal because unused data should not be compiled in the first
place. I believe this should be controlled by BL*_SOURCES in Makefiles,
not by linker scripts.
I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3,
BL31, BL31 for plat=uniphier. I did not see any more unexpected
code addition.
The bss section has bigger alignment. I added BSS_ALIGN for this.
Currently, SORT_BY_ALIGNMENT() is missing in sp_min.ld.S, and with this
change, the BSS symbols in SP_MIN will be sorted by the alignment.
This is not a big deal (or, even better in terms of the image size).
Change-Id: I680ee61f84067a559bac0757f9d03e73119beb33
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 0a0a7a9a | 26-Mar-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
linker_script: replace common read-only data with RODATA_COMMON
The common section data are repeated in many linker scripts (often
twice in each script to support SEPARATE_CODE_AND_RODATA). When you
linker_script: replace common read-only data with RODATA_COMMON
The common section data are repeated in many linker scripts (often
twice in each script to support SEPARATE_CODE_AND_RODATA). When you
add a new read-only data section, you end up with touching lots of
places.
After this commit, you will only need to touch bl_common.ld.h when
you add a new section to RODATA_COMMON.
Replace a series of RO section with RODATA_COMMON, which contains
6 sections, some of which did not exist before.
This is not a big deal because unneeded data should not be compiled
in the first place. I believe this should be controlled by BL*_SOURCES
in Makefiles, not by linker scripts.
When I was working on this commit, the BL1 image size increased
due to the fconf_populator. Commit c452ba159c14 ("fconf: exclude
fconf_dyn_cfg_getter.c from BL1_SOURCES") fixed this issue.
I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3,
BL31, BL31 for plat=uniphier. I did not see any more unexpected
code addition.
Change-Id: I5d14d60dbe3c821765bce3ae538968ef266f1460
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| c6e0a64d | 31-Oct-2019 |
James Liao <jamesjj.liao@mediatek.com> |
mediatek: mt8183: Fix AARCH64 init fail on CPU0
CPU0 is default on, so it doesn't need to run pwr_domain_on() at
boot. CPU0 AARCH64 will be set in pwr_domain_suspend(), but it may
encounter race con
mediatek: mt8183: Fix AARCH64 init fail on CPU0
CPU0 is default on, so it doesn't need to run pwr_domain_on() at
boot. CPU0 AARCH64 will be set in pwr_domain_suspend(), but it may
encounter race condition with other CPUs.
Now AARCH64 will be set with cluster on in pwr_domain_on(), and
all CPUs on this cluster will be set together. It doesn't need to
set AARCH64 again in pwr_domain_suspend(), so the race condition
can be avoided.
Change-Id: I5693ad56e4901f82badb0fc0d8d13e4c9acfe648
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
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