1/* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/bl_common.ld.h> 8#include <lib/xlat_tables/xlat_tables_defs.h> 9 10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12ENTRY(tsp_entrypoint) 13 14 15MEMORY { 16 RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE 17} 18 19 20SECTIONS 21{ 22 . = BL32_BASE; 23 ASSERT(. == ALIGN(PAGE_SIZE), 24 "BL32_BASE address is not aligned on a page boundary.") 25 26#if SEPARATE_CODE_AND_RODATA 27 .text . : { 28 __TEXT_START__ = .; 29 *tsp_entrypoint.o(.text*) 30 *(.text*) 31 *(.vectors) 32 . = ALIGN(PAGE_SIZE); 33 __TEXT_END__ = .; 34 } >RAM 35 36 .rodata . : { 37 __RODATA_START__ = .; 38 *(.rodata*) 39 40 GOT 41 42 . = ALIGN(PAGE_SIZE); 43 __RODATA_END__ = .; 44 } >RAM 45#else 46 ro . : { 47 __RO_START__ = .; 48 *tsp_entrypoint.o(.text*) 49 *(.text*) 50 *(.rodata*) 51 52 GOT 53 54 *(.vectors) 55 56 __RO_END_UNALIGNED__ = .; 57 /* 58 * Memory page(s) mapped to this section will be marked as 59 * read-only, executable. No RW data from the next section must 60 * creep in. Ensure the rest of the current memory page is unused. 61 */ 62 . = ALIGN(PAGE_SIZE); 63 __RO_END__ = .; 64 } >RAM 65#endif 66 67 /* 68 * Define a linker symbol to mark start of the RW memory area for this 69 * image. 70 */ 71 __RW_START__ = . ; 72 73 .data . : { 74 __DATA_START__ = .; 75 *(.data*) 76 __DATA_END__ = .; 77 } >RAM 78 79 /* 80 * .rela.dyn needs to come after .data for the read-elf utility to parse 81 * this section correctly. Ensure 8-byte alignment so that the fields of 82 * RELA data structure are aligned. 83 */ 84 . = ALIGN(8); 85 __RELA_START__ = .; 86 .rela.dyn . : { 87 } >RAM 88 __RELA_END__ = .; 89 90#ifdef TSP_PROGBITS_LIMIT 91 ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.") 92#endif 93 94 stacks (NOLOAD) : { 95 __STACKS_START__ = .; 96 *(tzfw_normal_stacks) 97 __STACKS_END__ = .; 98 } >RAM 99 100 /* 101 * The .bss section gets initialised to 0 at runtime. 102 * Its base address should be 16-byte aligned for better performance of the 103 * zero-initialization code. 104 */ 105 .bss : ALIGN(16) { 106 __BSS_START__ = .; 107 *(SORT_BY_ALIGNMENT(.bss*)) 108 *(COMMON) 109 __BSS_END__ = .; 110 } >RAM 111 112 XLAT_TABLE_SECTION >RAM 113 114#if USE_COHERENT_MEM 115 /* 116 * The base address of the coherent memory section must be page-aligned (4K) 117 * to guarantee that the coherent data are stored on their own pages and 118 * are not mixed with normal data. This is required to set up the correct 119 * memory attributes for the coherent data page tables. 120 */ 121 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 122 __COHERENT_RAM_START__ = .; 123 *(tzfw_coherent_mem) 124 __COHERENT_RAM_END_UNALIGNED__ = .; 125 /* 126 * Memory page(s) mapped to this section will be marked 127 * as device memory. No other unexpected data must creep in. 128 * Ensure the rest of the current memory page is unused. 129 */ 130 . = ALIGN(PAGE_SIZE); 131 __COHERENT_RAM_END__ = .; 132 } >RAM 133#endif 134 135 /* 136 * Define a linker symbol to mark the end of the RW memory area for this 137 * image. 138 */ 139 __RW_END__ = .; 140 __BL32_END__ = .; 141 142 /DISCARD/ : { 143 *(.dynsym .dynstr .hash .gnu.hash) 144 } 145 146 __BSS_SIZE__ = SIZEOF(.bss); 147#if USE_COHERENT_MEM 148 __COHERENT_RAM_UNALIGNED_SIZE__ = 149 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 150#endif 151 152 ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.") 153} 154