1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/arm/gic_common.h> 14 15 #include "../common/gic_common_private.h" 16 #include "gicv3_private.h" 17 18 /****************************************************************************** 19 * This function marks the core as awake in the re-distributor and 20 * ensures that the interface is active. 21 *****************************************************************************/ 22 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) 23 { 24 /* 25 * The WAKER_PS_BIT should be changed to 0 26 * only when WAKER_CA_BIT is 1. 27 */ 28 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U); 29 30 /* Mark the connected core as awake */ 31 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); 32 33 /* Wait till the WAKER_CA_BIT changes to 0 */ 34 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) { 35 } 36 } 37 38 /****************************************************************************** 39 * This function marks the core as asleep in the re-distributor and ensures 40 * that the interface is quiescent. 41 *****************************************************************************/ 42 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) 43 { 44 /* Mark the connected core as asleep */ 45 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); 46 47 /* Wait till the WAKER_CA_BIT changes to 1 */ 48 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) { 49 } 50 } 51 52 /******************************************************************************* 53 * This function probes the Redistributor frames when the driver is initialised 54 * and saves their base addresses. These base addresses are used later to 55 * initialise each Redistributor interface. 56 ******************************************************************************/ 57 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 58 unsigned int rdistif_num, 59 uintptr_t gicr_base, 60 mpidr_hash_fn mpidr_to_core_pos) 61 { 62 u_register_t mpidr; 63 unsigned int proc_num; 64 uint64_t typer_val; 65 uintptr_t rdistif_base = gicr_base; 66 67 assert(rdistif_base_addrs != NULL); 68 69 /* 70 * Iterate over the Redistributor frames. Store the base address of each 71 * frame in the platform provided array. Use the "Processor Number" 72 * field to index into the array if the platform has not provided a hash 73 * function to convert an MPIDR (obtained from the "Affinity Value" 74 * field into a linear index. 75 */ 76 do { 77 typer_val = gicr_read_typer(rdistif_base); 78 if (mpidr_to_core_pos != NULL) { 79 mpidr = mpidr_from_gicr_typer(typer_val); 80 proc_num = mpidr_to_core_pos(mpidr); 81 } else { 82 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & 83 TYPER_PROC_NUM_MASK; 84 } 85 86 if (proc_num < rdistif_num) { 87 rdistif_base_addrs[proc_num] = rdistif_base; 88 } 89 90 rdistif_base += (1U << GICR_PCPUBASE_SHIFT); 91 } while ((typer_val & TYPER_LAST_BIT) == 0U); 92 } 93 94 /******************************************************************************* 95 * Helper function to configure the default attributes of (E)SPIs. 96 ******************************************************************************/ 97 void gicv3_spis_config_defaults(uintptr_t gicd_base) 98 { 99 unsigned int i, num_ints; 100 #if GIC_EXT_INTID 101 unsigned int num_eints; 102 #endif 103 unsigned int typer_reg = gicd_read_typer(gicd_base); 104 105 /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */ 106 num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 107 108 /* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */ 109 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) { 110 gicd_write_igroupr(gicd_base, i, ~0U); 111 } 112 113 #if GIC_EXT_INTID 114 /* Check if extended SPI range is implemented */ 115 if ((typer_reg & TYPER_ESPI) != 0U) { 116 /* 117 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095 118 */ 119 num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 120 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID - 1; 121 122 for (i = MIN_ESPI_ID; i < num_eints; 123 i += (1U << IGROUPR_SHIFT)) { 124 gicd_write_igroupr(gicd_base, i, ~0U); 125 } 126 } else { 127 num_eints = 0U; 128 } 129 #endif 130 131 /* Setup the default (E)SPI priorities doing four at a time */ 132 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) { 133 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); 134 } 135 136 #if GIC_EXT_INTID 137 for (i = MIN_ESPI_ID; i < num_eints; 138 i += (1U << IPRIORITYR_SHIFT)) { 139 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); 140 } 141 #endif 142 /* 143 * Treat all (E)SPIs as level triggered by default, write 16 at a time 144 */ 145 for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) { 146 gicd_write_icfgr(gicd_base, i, 0U); 147 } 148 149 #if GIC_EXT_INTID 150 for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) { 151 gicd_write_icfgr(gicd_base, i, 0U); 152 } 153 #endif 154 } 155 156 /******************************************************************************* 157 * Helper function to configure properties of secure (E)SPIs 158 ******************************************************************************/ 159 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 160 const interrupt_prop_t *interrupt_props, 161 unsigned int interrupt_props_num) 162 { 163 unsigned int i; 164 const interrupt_prop_t *current_prop; 165 unsigned long long gic_affinity_val; 166 unsigned int ctlr_enable = 0U; 167 168 /* Make sure there's a valid property array */ 169 if (interrupt_props_num > 0U) { 170 assert(interrupt_props != NULL); 171 } 172 173 for (i = 0U; i < interrupt_props_num; i++) { 174 current_prop = &interrupt_props[i]; 175 176 unsigned int intr_num = current_prop->intr_num; 177 178 /* Skip SGI, (E)PPI and LPI interrupts */ 179 if (!IS_SPI(intr_num)) { 180 continue; 181 } 182 183 /* Configure this interrupt as a secure interrupt */ 184 gicd_clr_igroupr(gicd_base, intr_num); 185 186 /* Configure this interrupt as G0 or a G1S interrupt */ 187 assert((current_prop->intr_grp == INTR_GROUP0) || 188 (current_prop->intr_grp == INTR_GROUP1S)); 189 190 if (current_prop->intr_grp == INTR_GROUP1S) { 191 gicd_set_igrpmodr(gicd_base, intr_num); 192 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 193 } else { 194 gicd_clr_igrpmodr(gicd_base, intr_num); 195 ctlr_enable |= CTLR_ENABLE_G0_BIT; 196 } 197 198 /* Set interrupt configuration */ 199 gicd_set_icfgr(gicd_base, intr_num, current_prop->intr_cfg); 200 201 /* Set the priority of this interrupt */ 202 gicd_set_ipriorityr(gicd_base, intr_num, 203 current_prop->intr_pri); 204 205 /* Target (E)SPIs to the primary CPU */ 206 gic_affinity_val = 207 gicd_irouter_val_from_mpidr(read_mpidr(), 0U); 208 gicd_write_irouter(gicd_base, intr_num, 209 gic_affinity_val); 210 211 /* Enable this interrupt */ 212 gicd_set_isenabler(gicd_base, intr_num); 213 } 214 215 return ctlr_enable; 216 } 217 218 /******************************************************************************* 219 * Helper function to configure the default attributes of (E)SPIs 220 ******************************************************************************/ 221 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) 222 { 223 unsigned int i, ppi_regs_num, regs_num; 224 225 #if GIC_EXT_INTID 226 /* Calculate number of PPI registers */ 227 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 228 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 229 /* All other values except PPInum [0-2] are reserved */ 230 if (ppi_regs_num > 3U) { 231 ppi_regs_num = 1U; 232 } 233 #else 234 ppi_regs_num = 1U; 235 #endif 236 /* 237 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 238 * This is a more scalable approach as it avoids clearing 239 * the enable bits in the GICD_CTLR. 240 */ 241 for (i = 0U; i < ppi_regs_num; ++i) { 242 gicr_write_icenabler(gicr_base, i, ~0U); 243 } 244 245 /* Wait for pending writes to GICR_ICENABLER */ 246 gicr_wait_for_pending_write(gicr_base); 247 248 /* 32 interrupt IDs per GICR_IGROUPR register */ 249 for (i = 0U; i < ppi_regs_num; ++i) { 250 /* Treat all SGIs/(E)PPIs as G1NS by default */ 251 gicr_write_igroupr(gicr_base, i, ~0U); 252 } 253 254 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 255 regs_num = ppi_regs_num << 3; 256 for (i = 0U; i < regs_num; ++i) { 257 /* Setup the default (E)PPI/SGI priorities doing 4 at a time */ 258 gicr_write_ipriorityr(gicr_base, i, GICD_IPRIORITYR_DEF_VAL); 259 } 260 261 /* 16 interrupt IDs per GICR_ICFGR register */ 262 regs_num = ppi_regs_num << 1; 263 for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) { 264 /* Configure all (E)PPIs as level triggered by default */ 265 gicr_write_icfgr(gicr_base, i, 0U); 266 } 267 } 268 269 /******************************************************************************* 270 * Helper function to configure properties of secure G0 and G1S (E)PPIs and SGIs 271 ******************************************************************************/ 272 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 273 const interrupt_prop_t *interrupt_props, 274 unsigned int interrupt_props_num) 275 { 276 unsigned int i; 277 const interrupt_prop_t *current_prop; 278 unsigned int ctlr_enable = 0U; 279 280 /* Make sure there's a valid property array */ 281 if (interrupt_props_num > 0U) { 282 assert(interrupt_props != NULL); 283 } 284 285 for (i = 0U; i < interrupt_props_num; i++) { 286 current_prop = &interrupt_props[i]; 287 288 unsigned int intr_num = current_prop->intr_num; 289 290 /* Skip (E)SPI interrupt */ 291 if (!IS_SGI_PPI(intr_num)) { 292 continue; 293 } 294 295 /* Configure this interrupt as a secure interrupt */ 296 gicr_clr_igroupr(gicr_base, intr_num); 297 298 /* Configure this interrupt as G0 or a G1S interrupt */ 299 assert((current_prop->intr_grp == INTR_GROUP0) || 300 (current_prop->intr_grp == INTR_GROUP1S)); 301 302 if (current_prop->intr_grp == INTR_GROUP1S) { 303 gicr_set_igrpmodr(gicr_base, intr_num); 304 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 305 } else { 306 gicr_clr_igrpmodr(gicr_base, intr_num); 307 ctlr_enable |= CTLR_ENABLE_G0_BIT; 308 } 309 310 /* Set the priority of this interrupt */ 311 gicr_set_ipriorityr(gicr_base, intr_num, 312 current_prop->intr_pri); 313 314 /* 315 * Set interrupt configuration for (E)PPIs. 316 * Configurations for SGIs 0-15 are ignored. 317 */ 318 if (intr_num >= MIN_PPI_ID) { 319 gicr_set_icfgr(gicr_base, intr_num, 320 current_prop->intr_cfg); 321 } 322 323 /* Enable this interrupt */ 324 gicr_set_isenabler(gicr_base, intr_num); 325 } 326 327 return ctlr_enable; 328 } 329