1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GICV3_H 8 #define GICV3_H 9 10 /******************************************************************************* 11 * GICv3 and 3.1 miscellaneous definitions 12 ******************************************************************************/ 13 /* Interrupt group definitions */ 14 #define INTR_GROUP1S U(0) 15 #define INTR_GROUP0 U(1) 16 #define INTR_GROUP1NS U(2) 17 18 /* Interrupt IDs reported by the HPPIR and IAR registers */ 19 #define PENDING_G1S_INTID U(1020) 20 #define PENDING_G1NS_INTID U(1021) 21 22 /* Constant to categorize LPI interrupt */ 23 #define MIN_LPI_ID U(8192) 24 25 /* GICv3 can only target up to 16 PEs with SGI */ 26 #define GICV3_MAX_SGI_TARGETS U(16) 27 28 /* PPIs INTIDs 16-31 */ 29 #define MAX_PPI_ID U(31) 30 31 #if GIC_EXT_INTID 32 33 /* GICv3.1 extended PPIs INTIDs 1056-1119 */ 34 #define MIN_EPPI_ID U(1056) 35 #define MAX_EPPI_ID U(1119) 36 37 /* Total number of GICv3.1 EPPIs */ 38 #define TOTAL_EPPI_INTR_NUM (MAX_EPPI_ID - MIN_EPPI_ID + U(1)) 39 40 /* Total number of GICv3.1 PPIs and EPPIs */ 41 #define TOTAL_PRIVATE_INTR_NUM (TOTAL_PCPU_INTR_NUM + TOTAL_EPPI_INTR_NUM) 42 43 /* GICv3.1 extended SPIs INTIDs 4096 - 5119 */ 44 #define MIN_ESPI_ID U(4096) 45 #define MAX_ESPI_ID U(5119) 46 47 /* Total number of GICv3.1 ESPIs */ 48 #define TOTAL_ESPI_INTR_NUM (MAX_ESPI_ID - MIN_ESPI_ID + U(1)) 49 50 /* Total number of GICv3.1 SPIs and ESPIs */ 51 #define TOTAL_SHARED_INTR_NUM (TOTAL_SPI_INTR_NUM + TOTAL_ESPI_INTR_NUM) 52 53 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 54 #define IS_SGI_PPI(id) (((id) <= MAX_PPI_ID) || \ 55 (((id) >= MIN_EPPI_ID) && \ 56 ((id) <= MAX_EPPI_ID))) 57 58 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 59 #define IS_SPI(id) ((((id) >= MIN_SPI_ID) && \ 60 ((id) <= MAX_SPI_ID)) || \ 61 (((id) >= MIN_ESPI_ID) && \ 62 ((id) <= MAX_ESPI_ID))) 63 #else /* GICv3 */ 64 65 /* Total number of GICv3 PPIs */ 66 #define TOTAL_PRIVATE_INTR_NUM TOTAL_PCPU_INTR_NUM 67 68 /* Total number of GICv3 SPIs */ 69 #define TOTAL_SHARED_INTR_NUM TOTAL_SPI_INTR_NUM 70 71 /* SGIs: 0-15, PPIs: 16-31 */ 72 #define IS_SGI_PPI(id) ((id) <= MAX_PPI_ID) 73 74 /* SPIs: 32-1019 */ 75 #define IS_SPI(id) (((id) >= MIN_SPI_ID) && ((id) <= MAX_SPI_ID)) 76 77 #endif /* GIC_EXT_INTID */ 78 79 /******************************************************************************* 80 * GICv3 and 3.1 specific Distributor interface register offsets and constants 81 ******************************************************************************/ 82 #define GICD_TYPER2 U(0x0c) 83 #define GICD_STATUSR U(0x10) 84 #define GICD_SETSPI_NSR U(0x40) 85 #define GICD_CLRSPI_NSR U(0x48) 86 #define GICD_SETSPI_SR U(0x50) 87 #define GICD_CLRSPI_SR U(0x58) 88 #define GICD_IGRPMODR U(0xd00) 89 #define GICD_IGROUPRE U(0x1000) 90 #define GICD_ISENABLERE U(0x1200) 91 #define GICD_ICENABLERE U(0x1400) 92 #define GICD_ISPENDRE U(0x1600) 93 #define GICD_ICPENDRE U(0x1800) 94 #define GICD_ISACTIVERE U(0x1a00) 95 #define GICD_ICACTIVERE U(0x1c00) 96 #define GICD_IPRIORITYRE U(0x2000) 97 #define GICD_ICFGRE U(0x3000) 98 #define GICD_IGRPMODRE U(0x3400) 99 #define GICD_NSACRE U(0x3600) 100 /* 101 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt ID 102 * and n >= 32, making the effective offset as 0x6100 103 */ 104 #define GICD_IROUTER U(0x6000) 105 #define GICD_IROUTERE U(0x8000) 106 107 #define GICD_PIDR2_GICV3 U(0xffe8) 108 109 #define IGRPMODR_SHIFT 5 110 111 /* GICD_CTLR bit definitions */ 112 #define CTLR_ENABLE_G1NS_SHIFT 1 113 #define CTLR_ENABLE_G1S_SHIFT 2 114 #define CTLR_ARE_S_SHIFT 4 115 #define CTLR_ARE_NS_SHIFT 5 116 #define CTLR_DS_SHIFT 6 117 #define CTLR_E1NWF_SHIFT 7 118 #define GICD_CTLR_RWP_SHIFT 31 119 120 #define CTLR_ENABLE_G1NS_MASK U(0x1) 121 #define CTLR_ENABLE_G1S_MASK U(0x1) 122 #define CTLR_ARE_S_MASK U(0x1) 123 #define CTLR_ARE_NS_MASK U(0x1) 124 #define CTLR_DS_MASK U(0x1) 125 #define CTLR_E1NWF_MASK U(0x1) 126 #define GICD_CTLR_RWP_MASK U(0x1) 127 128 #define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT) 129 #define CTLR_ENABLE_G1S_BIT BIT_32(CTLR_ENABLE_G1S_SHIFT) 130 #define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT) 131 #define CTLR_ARE_NS_BIT BIT_32(CTLR_ARE_NS_SHIFT) 132 #define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT) 133 #define CTLR_E1NWF_BIT BIT_32(CTLR_E1NWF_SHIFT) 134 #define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT) 135 136 /* GICD_IROUTER shifts and masks */ 137 #define IROUTER_SHIFT 0 138 #define IROUTER_IRM_SHIFT 31 139 #define IROUTER_IRM_MASK U(0x1) 140 141 #define GICV3_IRM_PE U(0) 142 #define GICV3_IRM_ANY U(1) 143 144 #define NUM_OF_DIST_REGS 30 145 146 /* GICD_TYPER shifts and masks */ 147 #define TYPER_ESPI U(1 << 8) 148 #define TYPER_DVIS U(1 << 18) 149 #define TYPER_ESPI_RANGE_MASK U(0x1f) 150 #define TYPER_ESPI_RANGE_SHIFT U(27) 151 #define TYPER_ESPI_RANGE U(TYPER_ESPI_MASK << TYPER_ESPI_SHIFT) 152 153 /******************************************************************************* 154 * Common GIC Redistributor interface registers & constants 155 ******************************************************************************/ 156 #if GIC_ENABLE_V4_EXTN 157 #define GICR_PCPUBASE_SHIFT 0x12 158 #else 159 #define GICR_PCPUBASE_SHIFT 0x11 160 #endif 161 #define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */ 162 #define GICR_CTLR U(0x0) 163 #define GICR_IIDR U(0x04) 164 #define GICR_TYPER U(0x08) 165 #define GICR_STATUSR U(0x10) 166 #define GICR_WAKER U(0x14) 167 #define GICR_PROPBASER U(0x70) 168 #define GICR_PENDBASER U(0x78) 169 #define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + U(0x80)) 170 #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + U(0x100)) 171 #define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + U(0x180)) 172 #define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + U(0x200)) 173 #define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + U(0x280)) 174 #define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + U(0x300)) 175 #define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + U(0x380)) 176 #define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + U(0x400)) 177 #define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + U(0xc00)) 178 #define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + U(0xc04)) 179 #define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + U(0xd00)) 180 #define GICR_NSACR (GICR_SGIBASE_OFFSET + U(0xe00)) 181 182 #define GICR_IGROUPR GICR_IGROUPR0 183 #define GICR_ISENABLER GICR_ISENABLER0 184 #define GICR_ICENABLER GICR_ICENABLER0 185 #define GICR_ISPENDR GICR_ISPENDR0 186 #define GICR_ICPENDR GICR_ICPENDR0 187 #define GICR_ISACTIVER GICR_ISACTIVER0 188 #define GICR_ICACTIVER GICR_ICACTIVER0 189 #define GICR_ICFGR GICR_ICFGR0 190 #define GICR_IGRPMODR GICR_IGRPMODR0 191 192 /* GICR_CTLR bit definitions */ 193 #define GICR_CTLR_UWP_SHIFT 31 194 #define GICR_CTLR_UWP_MASK U(0x1) 195 #define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT) 196 #define GICR_CTLR_RWP_SHIFT 3 197 #define GICR_CTLR_RWP_MASK U(0x1) 198 #define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT) 199 #define GICR_CTLR_EN_LPIS_BIT BIT_32(0) 200 201 /* GICR_WAKER bit definitions */ 202 #define WAKER_CA_SHIFT 2 203 #define WAKER_PS_SHIFT 1 204 205 #define WAKER_CA_MASK U(0x1) 206 #define WAKER_PS_MASK U(0x1) 207 208 #define WAKER_CA_BIT BIT_32(WAKER_CA_SHIFT) 209 #define WAKER_PS_BIT BIT_32(WAKER_PS_SHIFT) 210 211 /* GICR_TYPER bit definitions */ 212 #define TYPER_AFF_VAL_SHIFT 32 213 #define TYPER_PROC_NUM_SHIFT 8 214 #define TYPER_LAST_SHIFT 4 215 216 #define TYPER_AFF_VAL_MASK U(0xffffffff) 217 #define TYPER_PROC_NUM_MASK U(0xffff) 218 #define TYPER_LAST_MASK U(0x1) 219 220 #define TYPER_LAST_BIT BIT_32(TYPER_LAST_SHIFT) 221 222 #define TYPER_PPI_NUM_SHIFT U(27) 223 #define TYPER_PPI_NUM_MASK U(0x1f) 224 225 /******************************************************************************* 226 * GICv3 and 3.1 CPU interface registers & constants 227 ******************************************************************************/ 228 /* ICC_SRE bit definitions */ 229 #define ICC_SRE_EN_BIT BIT_32(3) 230 #define ICC_SRE_DIB_BIT BIT_32(2) 231 #define ICC_SRE_DFB_BIT BIT_32(1) 232 #define ICC_SRE_SRE_BIT BIT_32(0) 233 234 /* ICC_IGRPEN1_EL3 bit definitions */ 235 #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0 236 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1 237 238 #define IGRPEN1_EL3_ENABLE_G1NS_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1NS_SHIFT) 239 #define IGRPEN1_EL3_ENABLE_G1S_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1S_SHIFT) 240 241 /* ICC_IGRPEN0_EL1 bit definitions */ 242 #define IGRPEN1_EL1_ENABLE_G0_SHIFT 0 243 #define IGRPEN1_EL1_ENABLE_G0_BIT BIT_32(IGRPEN1_EL1_ENABLE_G0_SHIFT) 244 245 /* ICC_HPPIR0_EL1 bit definitions */ 246 #define HPPIR0_EL1_INTID_SHIFT 0 247 #define HPPIR0_EL1_INTID_MASK U(0xffffff) 248 249 /* ICC_HPPIR1_EL1 bit definitions */ 250 #define HPPIR1_EL1_INTID_SHIFT 0 251 #define HPPIR1_EL1_INTID_MASK U(0xffffff) 252 253 /* ICC_IAR0_EL1 bit definitions */ 254 #define IAR0_EL1_INTID_SHIFT 0 255 #define IAR0_EL1_INTID_MASK U(0xffffff) 256 257 /* ICC_IAR1_EL1 bit definitions */ 258 #define IAR1_EL1_INTID_SHIFT 0 259 #define IAR1_EL1_INTID_MASK U(0xffffff) 260 261 /* ICC SGI macros */ 262 #define SGIR_TGT_MASK ULL(0xffff) 263 #define SGIR_AFF1_SHIFT 16 264 #define SGIR_INTID_SHIFT 24 265 #define SGIR_INTID_MASK ULL(0xf) 266 #define SGIR_AFF2_SHIFT 32 267 #define SGIR_IRM_SHIFT 40 268 #define SGIR_IRM_MASK ULL(0x1) 269 #define SGIR_AFF3_SHIFT 48 270 #define SGIR_AFF_MASK ULL(0xf) 271 272 #define SGIR_IRM_TO_AFF U(0) 273 274 #define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \ 275 ((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \ 276 (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \ 277 (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \ 278 (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \ 279 (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \ 280 ((_tgt) & SGIR_TGT_MASK)) 281 282 /***************************************************************************** 283 * GICv3 and 3.1 ITS registers and constants 284 *****************************************************************************/ 285 #define GITS_CTLR U(0x0) 286 #define GITS_IIDR U(0x4) 287 #define GITS_TYPER U(0x8) 288 #define GITS_CBASER U(0x80) 289 #define GITS_CWRITER U(0x88) 290 #define GITS_CREADR U(0x90) 291 #define GITS_BASER U(0x100) 292 293 /* GITS_CTLR bit definitions */ 294 #define GITS_CTLR_ENABLED_BIT BIT_32(0) 295 #define GITS_CTLR_QUIESCENT_BIT BIT_32(1) 296 297 #ifndef __ASSEMBLER__ 298 299 #include <stdbool.h> 300 #include <stdint.h> 301 302 #include <arch_helpers.h> 303 #include <common/interrupt_props.h> 304 #include <drivers/arm/gic_common.h> 305 #include <lib/utils_def.h> 306 307 static inline bool gicv3_is_intr_id_special_identifier(unsigned int id) 308 { 309 return (id >= PENDING_G1S_INTID) && (id <= GIC_SPURIOUS_INTERRUPT); 310 } 311 312 /******************************************************************************* 313 * Helper GICv3 and 3.1 macros for SEL1 314 ******************************************************************************/ 315 static inline uint32_t gicv3_acknowledge_interrupt_sel1(void) 316 { 317 return (uint32_t)read_icc_iar1_el1() & IAR1_EL1_INTID_MASK; 318 } 319 320 static inline uint32_t gicv3_get_pending_interrupt_id_sel1(void) 321 { 322 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 323 } 324 325 static inline void gicv3_end_of_interrupt_sel1(unsigned int id) 326 { 327 write_icc_eoir1_el1(id); 328 } 329 330 /******************************************************************************* 331 * Helper GICv3 macros for EL3 332 ******************************************************************************/ 333 static inline uint32_t gicv3_acknowledge_interrupt(void) 334 { 335 return (uint32_t)read_icc_iar0_el1() & IAR0_EL1_INTID_MASK; 336 } 337 338 static inline void gicv3_end_of_interrupt(unsigned int id) 339 { 340 return write_icc_eoir0_el1(id); 341 } 342 343 /* 344 * This macro returns the total number of GICD/GICR registers corresponding to 345 * the register name 346 */ 347 #define GICD_NUM_REGS(reg_name) \ 348 DIV_ROUND_UP_2EVAL(TOTAL_SHARED_INTR_NUM, (1 << reg_name##_SHIFT)) 349 350 #define GICR_NUM_REGS(reg_name) \ 351 DIV_ROUND_UP_2EVAL(TOTAL_PRIVATE_INTR_NUM, (1 << reg_name##_SHIFT)) 352 353 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ 354 #define INT_ID_MASK U(0xffffff) 355 356 /******************************************************************************* 357 * This structure describes some of the implementation defined attributes of the 358 * GICv3 IP. It is used by the platform port to specify these attributes in order 359 * to initialise the GICV3 driver. The attributes are described below. 360 * 361 * The 'gicd_base' field contains the base address of the Distributor interface 362 * programmer's view. 363 * 364 * The 'gicr_base' field contains the base address of the Re-distributor 365 * interface programmer's view. 366 * 367 * The 'interrupt_props' field is a pointer to an array that enumerates secure 368 * interrupts and their properties. If this field is not NULL, both 369 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored. 370 * 371 * The 'interrupt_props_num' field contains the number of entries in the 372 * 'interrupt_props' array. If this field is non-zero, both 'g0_interrupt_num' 373 * and 'g1s_interrupt_num' are ignored. 374 * 375 * The 'rdistif_num' field contains the number of Redistributor interfaces the 376 * GIC implements. This is equal to the number of CPUs or CPU interfaces 377 * instantiated in the GIC. 378 * 379 * The 'rdistif_base_addrs' field is a pointer to an array that has an entry for 380 * storing the base address of the Redistributor interface frame of each CPU in 381 * the system. The size of the array = 'rdistif_num'. The base addresses are 382 * detected during driver initialisation. 383 * 384 * The 'mpidr_to_core_pos' field is a pointer to a hash function which the 385 * driver will use to convert an MPIDR value to a linear core index. This index 386 * will be used for accessing the 'rdistif_base_addrs' array. This is an 387 * optional field. A GICv3 implementation maps each MPIDR to a linear core index 388 * as well. This mapping can be found by reading the "Affinity Value" and 389 * "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the 390 * "Processor Numbers" are suitable to index into an array to access core 391 * specific information. If this not the case, the platform port must provide a 392 * hash function. Otherwise, the "Processor Number" field will be used to access 393 * the array elements. 394 ******************************************************************************/ 395 typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr); 396 397 typedef struct gicv3_driver_data { 398 uintptr_t gicd_base; 399 uintptr_t gicr_base; 400 const interrupt_prop_t *interrupt_props; 401 unsigned int interrupt_props_num; 402 unsigned int rdistif_num; 403 uintptr_t *rdistif_base_addrs; 404 mpidr_hash_fn mpidr_to_core_pos; 405 } gicv3_driver_data_t; 406 407 typedef struct gicv3_redist_ctx { 408 /* 64 bits registers */ 409 uint64_t gicr_propbaser; 410 uint64_t gicr_pendbaser; 411 412 /* 32 bits registers */ 413 uint32_t gicr_ctlr; 414 uint32_t gicr_igroupr[GICR_NUM_REGS(IGROUPR)]; 415 uint32_t gicr_isenabler[GICR_NUM_REGS(ISENABLER)]; 416 uint32_t gicr_ispendr[GICR_NUM_REGS(ISPENDR)]; 417 uint32_t gicr_isactiver[GICR_NUM_REGS(ISACTIVER)]; 418 uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)]; 419 uint32_t gicr_icfgr[GICR_NUM_REGS(ICFGR)]; 420 uint32_t gicr_igrpmodr[GICR_NUM_REGS(IGRPMODR)]; 421 uint32_t gicr_nsacr; 422 } gicv3_redist_ctx_t; 423 424 typedef struct gicv3_dist_ctx { 425 /* 64 bits registers */ 426 uint64_t gicd_irouter[TOTAL_SHARED_INTR_NUM]; 427 428 /* 32 bits registers */ 429 uint32_t gicd_ctlr; 430 uint32_t gicd_igroupr[GICD_NUM_REGS(IGROUPR)]; 431 uint32_t gicd_isenabler[GICD_NUM_REGS(ISENABLER)]; 432 uint32_t gicd_ispendr[GICD_NUM_REGS(ISPENDR)]; 433 uint32_t gicd_isactiver[GICD_NUM_REGS(ISACTIVER)]; 434 uint32_t gicd_ipriorityr[GICD_NUM_REGS(IPRIORITYR)]; 435 uint32_t gicd_icfgr[GICD_NUM_REGS(ICFGR)]; 436 uint32_t gicd_igrpmodr[GICD_NUM_REGS(IGRPMODR)]; 437 uint32_t gicd_nsacr[GICD_NUM_REGS(NSACR)]; 438 } gicv3_dist_ctx_t; 439 440 typedef struct gicv3_its_ctx { 441 /* 64 bits registers */ 442 uint64_t gits_cbaser; 443 uint64_t gits_cwriter; 444 uint64_t gits_baser[8]; 445 446 /* 32 bits registers */ 447 uint32_t gits_ctlr; 448 } gicv3_its_ctx_t; 449 450 /******************************************************************************* 451 * GICv3 EL3 driver API 452 ******************************************************************************/ 453 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data); 454 int gicv3_rdistif_probe(const uintptr_t gicr_frame); 455 void gicv3_distif_init(void); 456 void gicv3_rdistif_init(unsigned int proc_num); 457 void gicv3_rdistif_on(unsigned int proc_num); 458 void gicv3_rdistif_off(unsigned int proc_num); 459 void gicv3_cpuif_enable(unsigned int proc_num); 460 void gicv3_cpuif_disable(unsigned int proc_num); 461 unsigned int gicv3_get_pending_interrupt_type(void); 462 unsigned int gicv3_get_pending_interrupt_id(void); 463 unsigned int gicv3_get_interrupt_type(unsigned int id, 464 unsigned int proc_num); 465 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx); 466 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx); 467 /* 468 * gicv3_distif_post_restore and gicv3_distif_pre_save must be implemented if 469 * gicv3_distif_save and gicv3_rdistif_init_restore are used. If no 470 * implementation-defined sequence is needed at these steps, an empty function 471 * can be provided. 472 */ 473 void gicv3_distif_post_restore(unsigned int proc_num); 474 void gicv3_distif_pre_save(unsigned int proc_num); 475 void gicv3_rdistif_init_restore(unsigned int proc_num, const gicv3_redist_ctx_t * const rdist_ctx); 476 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx); 477 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx); 478 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx); 479 480 unsigned int gicv3_get_running_priority(void); 481 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num); 482 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num); 483 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num); 484 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 485 unsigned int priority); 486 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 487 unsigned int type); 488 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target); 489 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, 490 u_register_t mpidr); 491 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num); 492 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num); 493 unsigned int gicv3_set_pmr(unsigned int mask); 494 495 #endif /* __ASSEMBLER__ */ 496 #endif /* GICV3_H */ 497