1/* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/bl_common.ld.h> 8#include <lib/xlat_tables/xlat_tables_defs.h> 9 10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12ENTRY(bl2_entrypoint) 13 14MEMORY { 15 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE 16} 17 18 19SECTIONS 20{ 21 . = BL2_BASE; 22 ASSERT(. == ALIGN(PAGE_SIZE), 23 "BL2_BASE address is not aligned on a page boundary.") 24 25#if SEPARATE_CODE_AND_RODATA 26 .text . : { 27 __TEXT_START__ = .; 28 *bl2_entrypoint.o(.text*) 29 *(SORT_BY_ALIGNMENT(.text*)) 30 *(.vectors) 31 . = ALIGN(PAGE_SIZE); 32 __TEXT_END__ = .; 33 } >RAM 34 35 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 36 .ARM.extab . : { 37 *(.ARM.extab* .gnu.linkonce.armextab.*) 38 } >RAM 39 40 .ARM.exidx . : { 41 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 42 } >RAM 43 44 .rodata . : { 45 __RODATA_START__ = .; 46 *(SORT_BY_ALIGNMENT(.rodata*)) 47 48 FCONF_POPULATOR 49 PARSER_LIB_DESCS 50 51 . = ALIGN(PAGE_SIZE); 52 __RODATA_END__ = .; 53 } >RAM 54#else 55 ro . : { 56 __RO_START__ = .; 57 *bl2_entrypoint.o(.text*) 58 *(SORT_BY_ALIGNMENT(.text*)) 59 *(SORT_BY_ALIGNMENT(.rodata*)) 60 61 FCONF_POPULATOR 62 PARSER_LIB_DESCS 63 64 *(.vectors) 65 __RO_END_UNALIGNED__ = .; 66 /* 67 * Memory page(s) mapped to this section will be marked as 68 * read-only, executable. No RW data from the next section must 69 * creep in. Ensure the rest of the current memory page is unused. 70 */ 71 . = ALIGN(PAGE_SIZE); 72 __RO_END__ = .; 73 } >RAM 74#endif 75 76 /* 77 * Define a linker symbol to mark start of the RW memory area for this 78 * image. 79 */ 80 __RW_START__ = . ; 81 82 /* 83 * .data must be placed at a lower address than the stacks if the stack 84 * protector is enabled. Alternatively, the .data.stack_protector_canary 85 * section can be placed independently of the main .data section. 86 */ 87 .data . : { 88 __DATA_START__ = .; 89 *(SORT_BY_ALIGNMENT(.data*)) 90 __DATA_END__ = .; 91 } >RAM 92 93 stacks (NOLOAD) : { 94 __STACKS_START__ = .; 95 *(tzfw_normal_stacks) 96 __STACKS_END__ = .; 97 } >RAM 98 99 /* 100 * The .bss section gets initialised to 0 at runtime. 101 * Its base address should be 16-byte aligned for better performance of the 102 * zero-initialization code. 103 */ 104 .bss : ALIGN(16) { 105 __BSS_START__ = .; 106 *(SORT_BY_ALIGNMENT(.bss*)) 107 *(COMMON) 108 __BSS_END__ = .; 109 } >RAM 110 111 XLAT_TABLE_SECTION >RAM 112 113#if USE_COHERENT_MEM 114 /* 115 * The base address of the coherent memory section must be page-aligned (4K) 116 * to guarantee that the coherent data are stored on their own pages and 117 * are not mixed with normal data. This is required to set up the correct 118 * memory attributes for the coherent data page tables. 119 */ 120 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 121 __COHERENT_RAM_START__ = .; 122 *(tzfw_coherent_mem) 123 __COHERENT_RAM_END_UNALIGNED__ = .; 124 /* 125 * Memory page(s) mapped to this section will be marked 126 * as device memory. No other unexpected data must creep in. 127 * Ensure the rest of the current memory page is unused. 128 */ 129 . = ALIGN(PAGE_SIZE); 130 __COHERENT_RAM_END__ = .; 131 } >RAM 132#endif 133 134 /* 135 * Define a linker symbol to mark end of the RW memory area for this 136 * image. 137 */ 138 __RW_END__ = .; 139 __BL2_END__ = .; 140 141 __BSS_SIZE__ = SIZEOF(.bss); 142 143#if USE_COHERENT_MEM 144 __COHERENT_RAM_UNALIGNED_SIZE__ = 145 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 146#endif 147 148 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") 149} 150