1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/utils.h> 26 27 28 /******************************************************************************* 29 * Context management library initialisation routine. This library is used by 30 * runtime services to share pointers to 'cpu_context' structures for the secure 31 * and non-secure states. Management of the structures and their associated 32 * memory is not done by the context management library e.g. the PSCI service 33 * manages the cpu context used for entry from and exit to the non-secure state. 34 * The Secure payload dispatcher service manages the context(s) corresponding to 35 * the secure state. It also uses this library to get access to the non-secure 36 * state cpu context pointers. 37 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 38 * which will used for programming an entry into a lower EL. The same context 39 * will used to save state upon exception entry from that EL. 40 ******************************************************************************/ 41 void __init cm_init(void) 42 { 43 /* 44 * The context management library has only global data to intialize, but 45 * that will be done when the BSS is zeroed out 46 */ 47 } 48 49 /******************************************************************************* 50 * The following function initializes the cpu_context 'ctx' for 51 * first use, and sets the initial entrypoint state as specified by the 52 * entry_point_info structure. 53 * 54 * The security state to initialize is determined by the SECURE attribute 55 * of the entry_point_info. 56 * 57 * The EE and ST attributes are used to configure the endianness and secure 58 * timer availability for the new execution context. 59 * 60 * To prepare the register state for entry call cm_prepare_el3_exit() and 61 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 62 * cm_e1_sysreg_context_restore(). 63 ******************************************************************************/ 64 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 65 { 66 unsigned int security_state; 67 u_register_t scr_el3; 68 el3_state_t *state; 69 gp_regs_t *gp_regs; 70 u_register_t sctlr_elx, actlr_elx; 71 72 assert(ctx != NULL); 73 74 security_state = GET_SECURITY_STATE(ep->h.attr); 75 76 /* Clear any residual register values from the context */ 77 zeromem(ctx, sizeof(*ctx)); 78 79 /* 80 * SCR_EL3 was initialised during reset sequence in macro 81 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 82 * affect the next EL. 83 * 84 * The following fields are initially set to zero and then updated to 85 * the required value depending on the state of the SPSR_EL3 and the 86 * Security state and entrypoint attributes of the next EL. 87 */ 88 scr_el3 = read_scr(); 89 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 90 SCR_ST_BIT | SCR_HCE_BIT); 91 /* 92 * SCR_NS: Set the security state of the next EL. 93 */ 94 if (security_state != SECURE) 95 scr_el3 |= SCR_NS_BIT; 96 /* 97 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 98 * Exception level as specified by SPSR. 99 */ 100 if (GET_RW(ep->spsr) == MODE_RW_64) 101 scr_el3 |= SCR_RW_BIT; 102 /* 103 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 104 * Secure timer registers to EL3, from AArch64 state only, if specified 105 * by the entrypoint attributes. 106 */ 107 if (EP_GET_ST(ep->h.attr) != 0U) 108 scr_el3 |= SCR_ST_BIT; 109 110 #if !HANDLE_EA_EL3_FIRST 111 /* 112 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 113 * to EL3 when executing at a lower EL. When executing at EL3, External 114 * Aborts are taken to EL3. 115 */ 116 scr_el3 &= ~SCR_EA_BIT; 117 #endif 118 119 #if FAULT_INJECTION_SUPPORT 120 /* Enable fault injection from lower ELs */ 121 scr_el3 |= SCR_FIEN_BIT; 122 #endif 123 124 #if !CTX_INCLUDE_PAUTH_REGS 125 /* 126 * If the pointer authentication registers aren't saved during world 127 * switches the value of the registers can be leaked from the Secure to 128 * the Non-secure world. To prevent this, rather than enabling pointer 129 * authentication everywhere, we only enable it in the Non-secure world. 130 * 131 * If the Secure world wants to use pointer authentication, 132 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 133 */ 134 if (security_state == NON_SECURE) 135 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 136 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 137 138 /* 139 * Enable MTE support. Support is enabled unilaterally for the normal 140 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 141 * set. 142 */ 143 #if CTX_INCLUDE_MTE_REGS 144 assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX); 145 scr_el3 |= SCR_ATA_BIT; 146 #else 147 unsigned int mte = get_armv8_5_mte_support(); 148 if (mte == MTE_IMPLEMENTED_EL0) { 149 /* 150 * Can enable MTE across both worlds as no MTE registers are 151 * used 152 */ 153 scr_el3 |= SCR_ATA_BIT; 154 } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) { 155 /* 156 * Can only enable MTE in Non-Secure world without register 157 * saving 158 */ 159 scr_el3 |= SCR_ATA_BIT; 160 } 161 #endif 162 163 #ifdef IMAGE_BL31 164 /* 165 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 166 * indicated by the interrupt routing model for BL31. 167 */ 168 scr_el3 |= get_scr_el3_from_routing_model(security_state); 169 #endif 170 171 /* 172 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 173 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 174 * next mode is Hyp. 175 */ 176 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 177 || ((GET_RW(ep->spsr) != MODE_RW_64) 178 && (GET_M32(ep->spsr) == MODE32_hyp))) { 179 scr_el3 |= SCR_HCE_BIT; 180 } 181 182 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 183 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { 184 if (GET_RW(ep->spsr) != MODE_RW_64) { 185 ERROR("S-EL2 can not be used in AArch32."); 186 panic(); 187 } 188 189 scr_el3 |= SCR_EEL2_BIT; 190 } 191 192 /* 193 * Initialise SCTLR_EL1 to the reset value corresponding to the target 194 * execution state setting all fields rather than relying of the hw. 195 * Some fields have architecturally UNKNOWN reset values and these are 196 * set to zero. 197 * 198 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 199 * 200 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 201 * required by PSCI specification) 202 */ 203 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 204 if (GET_RW(ep->spsr) == MODE_RW_64) 205 sctlr_elx |= SCTLR_EL1_RES1; 206 else { 207 /* 208 * If the target execution state is AArch32 then the following 209 * fields need to be set. 210 * 211 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 212 * instructions are not trapped to EL1. 213 * 214 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 215 * instructions are not trapped to EL1. 216 * 217 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 218 * CP15DMB, CP15DSB, and CP15ISB instructions. 219 */ 220 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 221 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 222 } 223 224 #if ERRATA_A75_764081 225 /* 226 * If workaround of errata 764081 for Cortex-A75 is used then set 227 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 228 */ 229 sctlr_elx |= SCTLR_IESB_BIT; 230 #endif 231 232 /* 233 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 234 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 235 * are not part of the stored cpu_context. 236 */ 237 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 238 239 /* 240 * Base the context ACTLR_EL1 on the current value, as it is 241 * implementation defined. The context restore process will write 242 * the value from the context to the actual register and can cause 243 * problems for processor cores that don't expect certain bits to 244 * be zero. 245 */ 246 actlr_elx = read_actlr_el1(); 247 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 248 249 /* 250 * Populate EL3 state so that we've the right context 251 * before doing ERET 252 */ 253 state = get_el3state_ctx(ctx); 254 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 255 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 256 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 257 258 /* 259 * Store the X0-X7 value from the entrypoint into the context 260 * Use memcpy as we are in control of the layout of the structures 261 */ 262 gp_regs = get_gpregs_ctx(ctx); 263 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 264 } 265 266 /******************************************************************************* 267 * Enable architecture extensions on first entry to Non-secure world. 268 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 269 * it is zero. 270 ******************************************************************************/ 271 static void enable_extensions_nonsecure(bool el2_unused) 272 { 273 #if IMAGE_BL31 274 #if ENABLE_SPE_FOR_LOWER_ELS 275 spe_enable(el2_unused); 276 #endif 277 278 #if ENABLE_AMU 279 amu_enable(el2_unused); 280 #endif 281 282 #if ENABLE_SVE_FOR_NS 283 sve_enable(el2_unused); 284 #endif 285 286 #if ENABLE_MPAM_FOR_LOWER_ELS 287 mpam_enable(el2_unused); 288 #endif 289 #endif 290 } 291 292 /******************************************************************************* 293 * The following function initializes the cpu_context for a CPU specified by 294 * its `cpu_idx` for first use, and sets the initial entrypoint state as 295 * specified by the entry_point_info structure. 296 ******************************************************************************/ 297 void cm_init_context_by_index(unsigned int cpu_idx, 298 const entry_point_info_t *ep) 299 { 300 cpu_context_t *ctx; 301 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 302 cm_setup_context(ctx, ep); 303 } 304 305 /******************************************************************************* 306 * The following function initializes the cpu_context for the current CPU 307 * for first use, and sets the initial entrypoint state as specified by the 308 * entry_point_info structure. 309 ******************************************************************************/ 310 void cm_init_my_context(const entry_point_info_t *ep) 311 { 312 cpu_context_t *ctx; 313 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 314 cm_setup_context(ctx, ep); 315 } 316 317 /******************************************************************************* 318 * Prepare the CPU system registers for first entry into secure or normal world 319 * 320 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 321 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 322 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 323 * For all entries, the EL1 registers are initialized from the cpu_context 324 ******************************************************************************/ 325 void cm_prepare_el3_exit(uint32_t security_state) 326 { 327 u_register_t sctlr_elx, scr_el3, mdcr_el2; 328 cpu_context_t *ctx = cm_get_context(security_state); 329 bool el2_unused = false; 330 uint64_t hcr_el2 = 0U; 331 332 assert(ctx != NULL); 333 334 if (security_state == NON_SECURE) { 335 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 336 CTX_SCR_EL3); 337 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 338 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 339 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 340 CTX_SCTLR_EL1); 341 sctlr_elx &= SCTLR_EE_BIT; 342 sctlr_elx |= SCTLR_EL2_RES1; 343 #if ERRATA_A75_764081 344 /* 345 * If workaround of errata 764081 for Cortex-A75 is used 346 * then set SCTLR_EL2.IESB to enable Implicit Error 347 * Synchronization Barrier. 348 */ 349 sctlr_elx |= SCTLR_IESB_BIT; 350 #endif 351 write_sctlr_el2(sctlr_elx); 352 } else if (el_implemented(2) != EL_IMPL_NONE) { 353 el2_unused = true; 354 355 /* 356 * EL2 present but unused, need to disable safely. 357 * SCTLR_EL2 can be ignored in this case. 358 * 359 * Set EL2 register width appropriately: Set HCR_EL2 360 * field to match SCR_EL3.RW. 361 */ 362 if ((scr_el3 & SCR_RW_BIT) != 0U) 363 hcr_el2 |= HCR_RW_BIT; 364 365 /* 366 * For Armv8.3 pointer authentication feature, disable 367 * traps to EL2 when accessing key registers or using 368 * pointer authentication instructions from lower ELs. 369 */ 370 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 371 372 write_hcr_el2(hcr_el2); 373 374 /* 375 * Initialise CPTR_EL2 setting all fields rather than 376 * relying on the hw. All fields have architecturally 377 * UNKNOWN reset values. 378 * 379 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 380 * accesses to the CPACR_EL1 or CPACR from both 381 * Execution states do not trap to EL2. 382 * 383 * CPTR_EL2.TTA: Set to zero so that Non-secure System 384 * register accesses to the trace registers from both 385 * Execution states do not trap to EL2. 386 * 387 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 388 * to SIMD and floating-point functionality from both 389 * Execution states do not trap to EL2. 390 */ 391 write_cptr_el2(CPTR_EL2_RESET_VAL & 392 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 393 | CPTR_EL2_TFP_BIT)); 394 395 /* 396 * Initialise CNTHCTL_EL2. All fields are 397 * architecturally UNKNOWN on reset and are set to zero 398 * except for field(s) listed below. 399 * 400 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 401 * Hyp mode of Non-secure EL0 and EL1 accesses to the 402 * physical timer registers. 403 * 404 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 405 * Hyp mode of Non-secure EL0 and EL1 accesses to the 406 * physical counter registers. 407 */ 408 write_cnthctl_el2(CNTHCTL_RESET_VAL | 409 EL1PCEN_BIT | EL1PCTEN_BIT); 410 411 /* 412 * Initialise CNTVOFF_EL2 to zero as it resets to an 413 * architecturally UNKNOWN value. 414 */ 415 write_cntvoff_el2(0); 416 417 /* 418 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 419 * MPIDR_EL1 respectively. 420 */ 421 write_vpidr_el2(read_midr_el1()); 422 write_vmpidr_el2(read_mpidr_el1()); 423 424 /* 425 * Initialise VTTBR_EL2. All fields are architecturally 426 * UNKNOWN on reset. 427 * 428 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 429 * 2 address translation is disabled, cache maintenance 430 * operations depend on the VMID. 431 * 432 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 433 * translation is disabled. 434 */ 435 write_vttbr_el2(VTTBR_RESET_VAL & 436 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 437 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 438 439 /* 440 * Initialise MDCR_EL2, setting all fields rather than 441 * relying on hw. Some fields are architecturally 442 * UNKNOWN on reset. 443 * 444 * MDCR_EL2.HLP: Set to one so that event counter 445 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 446 * occurs on the increment that changes 447 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 448 * implemented. This bit is RES0 in versions of the 449 * architecture earlier than ARMv8.5, setting it to 1 450 * doesn't have any effect on them. 451 * 452 * MDCR_EL2.TTRF: Set to zero so that access to Trace 453 * Filter Control register TRFCR_EL1 at EL1 is not 454 * trapped to EL2. This bit is RES0 in versions of 455 * the architecture earlier than ARMv8.4. 456 * 457 * MDCR_EL2.HPMD: Set to one so that event counting is 458 * prohibited at EL2. This bit is RES0 in versions of 459 * the architecture earlier than ARMv8.1, setting it 460 * to 1 doesn't have any effect on them. 461 * 462 * MDCR_EL2.TPMS: Set to zero so that accesses to 463 * Statistical Profiling control registers from EL1 464 * do not trap to EL2. This bit is RES0 when SPE is 465 * not implemented. 466 * 467 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 468 * EL1 System register accesses to the Debug ROM 469 * registers are not trapped to EL2. 470 * 471 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 472 * System register accesses to the powerdown debug 473 * registers are not trapped to EL2. 474 * 475 * MDCR_EL2.TDA: Set to zero so that System register 476 * accesses to the debug registers do not trap to EL2. 477 * 478 * MDCR_EL2.TDE: Set to zero so that debug exceptions 479 * are not routed to EL2. 480 * 481 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 482 * Monitors. 483 * 484 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 485 * EL1 accesses to all Performance Monitors registers 486 * are not trapped to EL2. 487 * 488 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 489 * and EL1 accesses to the PMCR_EL0 or PMCR are not 490 * trapped to EL2. 491 * 492 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 493 * architecturally-defined reset value. 494 */ 495 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 496 MDCR_EL2_HPMD) | 497 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 498 >> PMCR_EL0_N_SHIFT)) & 499 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 500 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 501 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 502 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 503 MDCR_EL2_TPMCR_BIT); 504 505 write_mdcr_el2(mdcr_el2); 506 507 /* 508 * Initialise HSTR_EL2. All fields are architecturally 509 * UNKNOWN on reset. 510 * 511 * HSTR_EL2.T<n>: Set all these fields to zero so that 512 * Non-secure EL0 or EL1 accesses to System registers 513 * do not trap to EL2. 514 */ 515 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 516 /* 517 * Initialise CNTHP_CTL_EL2. All fields are 518 * architecturally UNKNOWN on reset. 519 * 520 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 521 * physical timer and prevent timer interrupts. 522 */ 523 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 524 ~(CNTHP_CTL_ENABLE_BIT)); 525 } 526 enable_extensions_nonsecure(el2_unused); 527 } 528 529 cm_el1_sysregs_context_restore(security_state); 530 cm_set_next_eret_context(security_state); 531 } 532 533 #if CTX_INCLUDE_EL2_REGS 534 /******************************************************************************* 535 * Save EL2 sysreg context 536 ******************************************************************************/ 537 void cm_el2_sysregs_context_save(uint32_t security_state) 538 { 539 u_register_t scr_el3 = read_scr(); 540 541 /* 542 * Always save the non-secure EL2 context, only save the 543 * S-EL2 context if S-EL2 is enabled. 544 */ 545 if ((security_state == NON_SECURE) || 546 ((scr_el3 & SCR_EEL2_BIT) != 0U)) { 547 cpu_context_t *ctx; 548 549 ctx = cm_get_context(security_state); 550 assert(ctx != NULL); 551 552 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 553 } 554 } 555 556 /******************************************************************************* 557 * Restore EL2 sysreg context 558 ******************************************************************************/ 559 void cm_el2_sysregs_context_restore(uint32_t security_state) 560 { 561 u_register_t scr_el3 = read_scr(); 562 563 /* 564 * Always restore the non-secure EL2 context, only restore the 565 * S-EL2 context if S-EL2 is enabled. 566 */ 567 if ((security_state == NON_SECURE) || 568 ((scr_el3 & SCR_EEL2_BIT) != 0U)) { 569 cpu_context_t *ctx; 570 571 ctx = cm_get_context(security_state); 572 assert(ctx != NULL); 573 574 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 575 } 576 } 577 #endif /* CTX_INCLUDE_EL2_REGS */ 578 579 /******************************************************************************* 580 * The next four functions are used by runtime services to save and restore 581 * EL1 context on the 'cpu_context' structure for the specified security 582 * state. 583 ******************************************************************************/ 584 void cm_el1_sysregs_context_save(uint32_t security_state) 585 { 586 cpu_context_t *ctx; 587 588 ctx = cm_get_context(security_state); 589 assert(ctx != NULL); 590 591 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 592 593 #if IMAGE_BL31 594 if (security_state == SECURE) 595 PUBLISH_EVENT(cm_exited_secure_world); 596 else 597 PUBLISH_EVENT(cm_exited_normal_world); 598 #endif 599 } 600 601 void cm_el1_sysregs_context_restore(uint32_t security_state) 602 { 603 cpu_context_t *ctx; 604 605 ctx = cm_get_context(security_state); 606 assert(ctx != NULL); 607 608 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 609 610 #if IMAGE_BL31 611 if (security_state == SECURE) 612 PUBLISH_EVENT(cm_entering_secure_world); 613 else 614 PUBLISH_EVENT(cm_entering_normal_world); 615 #endif 616 } 617 618 /******************************************************************************* 619 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 620 * given security state with the given entrypoint 621 ******************************************************************************/ 622 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 623 { 624 cpu_context_t *ctx; 625 el3_state_t *state; 626 627 ctx = cm_get_context(security_state); 628 assert(ctx != NULL); 629 630 /* Populate EL3 state so that ERET jumps to the correct entry */ 631 state = get_el3state_ctx(ctx); 632 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 633 } 634 635 /******************************************************************************* 636 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 637 * pertaining to the given security state 638 ******************************************************************************/ 639 void cm_set_elr_spsr_el3(uint32_t security_state, 640 uintptr_t entrypoint, uint32_t spsr) 641 { 642 cpu_context_t *ctx; 643 el3_state_t *state; 644 645 ctx = cm_get_context(security_state); 646 assert(ctx != NULL); 647 648 /* Populate EL3 state so that ERET jumps to the correct entry */ 649 state = get_el3state_ctx(ctx); 650 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 651 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 652 } 653 654 /******************************************************************************* 655 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 656 * pertaining to the given security state using the value and bit position 657 * specified in the parameters. It preserves all other bits. 658 ******************************************************************************/ 659 void cm_write_scr_el3_bit(uint32_t security_state, 660 uint32_t bit_pos, 661 uint32_t value) 662 { 663 cpu_context_t *ctx; 664 el3_state_t *state; 665 u_register_t scr_el3; 666 667 ctx = cm_get_context(security_state); 668 assert(ctx != NULL); 669 670 /* Ensure that the bit position is a valid one */ 671 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 672 673 /* Ensure that the 'value' is only a bit wide */ 674 assert(value <= 1U); 675 676 /* 677 * Get the SCR_EL3 value from the cpu context, clear the desired bit 678 * and set it to its new value. 679 */ 680 state = get_el3state_ctx(ctx); 681 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 682 scr_el3 &= ~(1U << bit_pos); 683 scr_el3 |= (u_register_t)value << bit_pos; 684 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 685 } 686 687 /******************************************************************************* 688 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 689 * given security state. 690 ******************************************************************************/ 691 u_register_t cm_get_scr_el3(uint32_t security_state) 692 { 693 cpu_context_t *ctx; 694 el3_state_t *state; 695 696 ctx = cm_get_context(security_state); 697 assert(ctx != NULL); 698 699 /* Populate EL3 state so that ERET jumps to the correct entry */ 700 state = get_el3state_ctx(ctx); 701 return read_ctx_reg(state, CTX_SCR_EL3); 702 } 703 704 /******************************************************************************* 705 * This function is used to program the context that's used for exception 706 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 707 * the required security state 708 ******************************************************************************/ 709 void cm_set_next_eret_context(uint32_t security_state) 710 { 711 cpu_context_t *ctx; 712 713 ctx = cm_get_context(security_state); 714 assert(ctx != NULL); 715 716 cm_set_next_context(ctx); 717 } 718