1/* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/bl_common.ld.h> 8#include <lib/xlat_tables/xlat_tables_defs.h> 9 10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12ENTRY(bl1_entrypoint) 13 14MEMORY { 15 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE 16 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE 17} 18 19SECTIONS 20{ 21 . = BL1_RO_BASE; 22 ASSERT(. == ALIGN(PAGE_SIZE), 23 "BL1_RO_BASE address is not aligned on a page boundary.") 24 25#if SEPARATE_CODE_AND_RODATA 26 .text . : { 27 __TEXT_START__ = .; 28 *bl1_entrypoint.o(.text*) 29 *(SORT_BY_ALIGNMENT(.text*)) 30 *(.vectors) 31 . = ALIGN(PAGE_SIZE); 32 __TEXT_END__ = .; 33 } >ROM 34 35 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 36 .ARM.extab . : { 37 *(.ARM.extab* .gnu.linkonce.armextab.*) 38 } >ROM 39 40 .ARM.exidx . : { 41 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 42 } >ROM 43 44 .rodata . : { 45 __RODATA_START__ = .; 46 *(SORT_BY_ALIGNMENT(.rodata*)) 47 48 PARSER_LIB_DESCS 49 CPU_OPS 50 51 /* 52 * No need to pad out the .rodata section to a page boundary. Next is 53 * the .data section, which can mapped in ROM with the same memory 54 * attributes as the .rodata section. 55 * 56 * Pad out to 16 bytes though as .data section needs to be 16 byte 57 * aligned and lld does not align the LMA to the aligment specified 58 * on the .data section. 59 */ 60 __RODATA_END__ = .; 61 . = ALIGN(16); 62 } >ROM 63#else 64 ro . : { 65 __RO_START__ = .; 66 *bl1_entrypoint.o(.text*) 67 *(SORT_BY_ALIGNMENT(.text*)) 68 *(SORT_BY_ALIGNMENT(.rodata*)) 69 70 PARSER_LIB_DESCS 71 CPU_OPS 72 73 *(.vectors) 74 __RO_END__ = .; 75 76 /* 77 * Pad out to 16 bytes as .data section needs to be 16 byte aligned and 78 * lld does not align the LMA to the aligment specified on the .data 79 * section. 80 */ 81 . = ALIGN(16); 82 } >ROM 83#endif 84 85 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 86 "cpu_ops not defined for this platform.") 87 88 . = BL1_RW_BASE; 89 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE), 90 "BL1_RW_BASE address is not aligned on a page boundary.") 91 92 /* 93 * The .data section gets copied from ROM to RAM at runtime. 94 * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes 95 * aligned regions in it. 96 * Its VMA must be page-aligned as it marks the first read/write page. 97 * 98 * It must be placed at a lower address than the stacks if the stack 99 * protector is enabled. Alternatively, the .data.stack_protector_canary 100 * section can be placed independently of the main .data section. 101 */ 102 .data . : ALIGN(16) { 103 __DATA_RAM_START__ = .; 104 *(SORT_BY_ALIGNMENT(.data*)) 105 __DATA_RAM_END__ = .; 106 } >RAM AT>ROM 107 108 stacks . (NOLOAD) : { 109 __STACKS_START__ = .; 110 *(tzfw_normal_stacks) 111 __STACKS_END__ = .; 112 } >RAM 113 114 /* 115 * The .bss section gets initialised to 0 at runtime. 116 * Its base address should be 16-byte aligned for better performance of the 117 * zero-initialization code. 118 */ 119 .bss : ALIGN(16) { 120 __BSS_START__ = .; 121 *(SORT_BY_ALIGNMENT(.bss*)) 122 *(COMMON) 123 __BSS_END__ = .; 124 } >RAM 125 126 XLAT_TABLE_SECTION >RAM 127 128#if USE_COHERENT_MEM 129 /* 130 * The base address of the coherent memory section must be page-aligned (4K) 131 * to guarantee that the coherent data are stored on their own pages and 132 * are not mixed with normal data. This is required to set up the correct 133 * memory attributes for the coherent data page tables. 134 */ 135 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 136 __COHERENT_RAM_START__ = .; 137 *(tzfw_coherent_mem) 138 __COHERENT_RAM_END_UNALIGNED__ = .; 139 /* 140 * Memory page(s) mapped to this section will be marked 141 * as device memory. No other unexpected data must creep in. 142 * Ensure the rest of the current memory page is unused. 143 */ 144 . = ALIGN(PAGE_SIZE); 145 __COHERENT_RAM_END__ = .; 146 } >RAM 147#endif 148 149 __BL1_RAM_START__ = ADDR(.data); 150 __BL1_RAM_END__ = .; 151 152 __DATA_ROM_START__ = LOADADDR(.data); 153 __DATA_SIZE__ = SIZEOF(.data); 154 155 /* 156 * The .data section is the last PROGBITS section so its end marks the end 157 * of BL1's actual content in Trusted ROM. 158 */ 159 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 160 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, 161 "BL1's ROM content has exceeded its limit.") 162 163 __BSS_SIZE__ = SIZEOF(.bss); 164 165#if USE_COHERENT_MEM 166 __COHERENT_RAM_UNALIGNED_SIZE__ = 167 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 168#endif 169 170 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") 171} 172