1/* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <context.h> 11 12#if CTX_INCLUDE_EL2_REGS 13 .global el2_sysregs_context_save 14 .global el2_sysregs_context_restore 15#endif 16 17 .global el1_sysregs_context_save 18 .global el1_sysregs_context_restore 19#if CTX_INCLUDE_FPREGS 20 .global fpregs_context_save 21 .global fpregs_context_restore 22#endif 23 .global save_gp_pmcr_pauth_regs 24 .global restore_gp_pmcr_pauth_regs 25 .global el3_exit 26 27#if CTX_INCLUDE_EL2_REGS 28 29/* ----------------------------------------------------- 30 * The following function strictly follows the AArch64 31 * PCS to use x9-x17 (temporary caller-saved registers) 32 * to save EL2 system register context. It assumes that 33 * 'x0' is pointing to a 'el2_sys_regs' structure where 34 * the register context will be saved. 35 * 36 * The following registers are not added. 37 * AMEVCNTVOFF0<n>_EL2 38 * AMEVCNTVOFF1<n>_EL2 39 * ICH_AP0R<n>_EL2 40 * ICH_AP1R<n>_EL2 41 * ICH_LR<n>_EL2 42 * ----------------------------------------------------- 43 */ 44 45func el2_sysregs_context_save 46 mrs x9, actlr_el2 47 mrs x10, afsr0_el2 48 stp x9, x10, [x0, #CTX_ACTLR_EL2] 49 50 mrs x11, afsr1_el2 51 mrs x12, amair_el2 52 stp x11, x12, [x0, #CTX_AFSR1_EL2] 53 54 mrs x13, cnthctl_el2 55 mrs x14, cnthp_ctl_el2 56 stp x13, x14, [x0, #CTX_CNTHCTL_EL2] 57 58 mrs x15, cnthp_cval_el2 59 mrs x16, cnthp_tval_el2 60 stp x15, x16, [x0, #CTX_CNTHP_CVAL_EL2] 61 62 mrs x17, cntvoff_el2 63 mrs x9, cptr_el2 64 stp x17, x9, [x0, #CTX_CNTVOFF_EL2] 65 66 mrs x10, dbgvcr32_el2 67 mrs x11, elr_el2 68 stp x10, x11, [x0, #CTX_DBGVCR32_EL2] 69 70 mrs x14, esr_el2 71 mrs x15, far_el2 72 stp x14, x15, [x0, #CTX_ESR_EL2] 73 74 mrs x16, fpexc32_el2 75 mrs x17, hacr_el2 76 stp x16, x17, [x0, #CTX_FPEXC32_EL2] 77 78 mrs x9, hcr_el2 79 mrs x10, hpfar_el2 80 stp x9, x10, [x0, #CTX_HCR_EL2] 81 82 mrs x11, hstr_el2 83 mrs x12, ICC_SRE_EL2 84 stp x11, x12, [x0, #CTX_HSTR_EL2] 85 86 mrs x13, ICH_HCR_EL2 87 mrs x14, ICH_VMCR_EL2 88 stp x13, x14, [x0, #CTX_ICH_HCR_EL2] 89 90 mrs x15, mair_el2 91 mrs x16, mdcr_el2 92 stp x15, x16, [x0, #CTX_MAIR_EL2] 93 94 mrs x17, PMSCR_EL2 95 mrs x9, sctlr_el2 96 stp x17, x9, [x0, #CTX_PMSCR_EL2] 97 98 mrs x10, spsr_el2 99 mrs x11, sp_el2 100 stp x10, x11, [x0, #CTX_SPSR_EL2] 101 102 mrs x12, tcr_el2 103 mrs x13, TRFCR_EL2 104 stp x12, x13, [x0, #CTX_TCR_EL2] 105 106 mrs x14, ttbr0_el2 107 mrs x15, vbar_el2 108 stp x14, x15, [x0, #CTX_TTBR0_EL2] 109 110 mrs x16, vmpidr_el2 111 mrs x17, vpidr_el2 112 stp x16, x17, [x0, #CTX_VMPIDR_EL2] 113 114 mrs x9, vtcr_el2 115 mrs x10, vttbr_el2 116 stp x9, x10, [x0, #CTX_VTCR_EL2] 117 118#if CTX_INCLUDE_MTE_REGS 119 mrs x11, TFSR_EL2 120 str x11, [x0, #CTX_TFSR_EL2] 121#endif 122 123#if ENABLE_MPAM_FOR_LOWER_ELS 124 mrs x9, MPAM2_EL2 125 mrs x10, MPAMHCR_EL2 126 stp x9, x10, [x0, #CTX_MPAM2_EL2] 127 128 mrs x11, MPAMVPM0_EL2 129 mrs x12, MPAMVPM1_EL2 130 stp x11, x12, [x0, #CTX_MPAMVPM0_EL2] 131 132 mrs x13, MPAMVPM2_EL2 133 mrs x14, MPAMVPM3_EL2 134 stp x13, x14, [x0, #CTX_MPAMVPM2_EL2] 135 136 mrs x15, MPAMVPM4_EL2 137 mrs x16, MPAMVPM5_EL2 138 stp x15, x16, [x0, #CTX_MPAMVPM4_EL2] 139 140 mrs x17, MPAMVPM6_EL2 141 mrs x9, MPAMVPM7_EL2 142 stp x17, x9, [x0, #CTX_MPAMVPM6_EL2] 143 144 mrs x10, MPAMVPMV_EL2 145 str x10, [x0, #CTX_MPAMVPMV_EL2] 146#endif 147 148 149#if ARM_ARCH_AT_LEAST(8, 6) 150 mrs x11, HAFGRTR_EL2 151 mrs x12, HDFGRTR_EL2 152 stp x11, x12, [x0, #CTX_HAFGRTR_EL2] 153 154 mrs x13, HDFGWTR_EL2 155 mrs x14, HFGITR_EL2 156 stp x13, x14, [x0, #CTX_HDFGWTR_EL2] 157 158 mrs x15, HFGRTR_EL2 159 mrs x16, HFGWTR_EL2 160 stp x15, x16, [x0, #CTX_HFGRTR_EL2] 161 162 mrs x17, CNTPOFF_EL2 163 str x17, [x0, #CTX_CNTPOFF_EL2] 164#endif 165 166#if ARM_ARCH_AT_LEAST(8, 4) 167 mrs x9, cnthps_ctl_el2 168 mrs x10, cnthps_cval_el2 169 stp x9, x10, [x0, #CTX_CNTHPS_CTL_EL2] 170 171 mrs x11, cnthps_tval_el2 172 mrs x12, cnthvs_ctl_el2 173 stp x11, x12, [x0, #CTX_CNTHPS_TVAL_EL2] 174 175 mrs x13, cnthvs_cval_el2 176 mrs x14, cnthvs_tval_el2 177 stp x13, x14, [x0, #CTX_CNTHVS_CVAL_EL2] 178 179 mrs x15, cnthv_ctl_el2 180 mrs x16, cnthv_cval_el2 181 stp x15, x16, [x0, #CTX_CNTHV_CTL_EL2] 182 183 mrs x17, cnthv_tval_el2 184 mrs x9, contextidr_el2 185 stp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2] 186 187 mrs x10, sder32_el2 188 str x10, [x0, #CTX_SDER32_EL2] 189 190 mrs x11, ttbr1_el2 191 str x11, [x0, #CTX_TTBR1_EL2] 192 193 mrs x12, vdisr_el2 194 str x12, [x0, #CTX_VDISR_EL2] 195 196 mrs x13, vncr_el2 197 str x13, [x0, #CTX_VNCR_EL2] 198 199 mrs x14, vsesr_el2 200 str x14, [x0, #CTX_VSESR_EL2] 201 202 mrs x15, vstcr_el2 203 str x15, [x0, #CTX_VSTCR_EL2] 204 205 mrs x16, vsttbr_el2 206 str x16, [x0, #CTX_VSTTBR_EL2] 207#endif 208 209#if ARM_ARCH_AT_LEAST(8, 5) 210 mrs x17, scxtnum_el2 211 str x17, [x0, #CTX_SCXTNUM_EL2] 212#endif 213 214 ret 215endfunc el2_sysregs_context_save 216 217/* ----------------------------------------------------- 218 * The following function strictly follows the AArch64 219 * PCS to use x9-x17 (temporary caller-saved registers) 220 * to restore EL2 system register context. It assumes 221 * that 'x0' is pointing to a 'el2_sys_regs' structure 222 * from where the register context will be restored 223 224 * The following registers are not restored 225 * AMEVCNTVOFF0<n>_EL2 226 * AMEVCNTVOFF1<n>_EL2 227 * ICH_AP0R<n>_EL2 228 * ICH_AP1R<n>_EL2 229 * ICH_LR<n>_EL2 230 * ----------------------------------------------------- 231 */ 232func el2_sysregs_context_restore 233 234 ldp x9, x10, [x0, #CTX_ACTLR_EL2] 235 msr actlr_el2, x9 236 msr afsr0_el2, x10 237 238 ldp x11, x12, [x0, #CTX_AFSR1_EL2] 239 msr afsr1_el2, x11 240 msr amair_el2, x12 241 242 ldp x13, x14, [x0, #CTX_CNTHCTL_EL2] 243 msr cnthctl_el2, x13 244 msr cnthp_ctl_el2, x14 245 246 ldp x15, x16, [x0, #CTX_CNTHP_CVAL_EL2] 247 msr cnthp_cval_el2, x15 248 msr cnthp_tval_el2, x16 249 250 ldp x17, x9, [x0, #CTX_CNTVOFF_EL2] 251 msr cntvoff_el2, x17 252 msr cptr_el2, x9 253 254 ldp x10, x11, [x0, #CTX_DBGVCR32_EL2] 255 msr dbgvcr32_el2, x10 256 msr elr_el2, x11 257 258 ldp x14, x15, [x0, #CTX_ESR_EL2] 259 msr esr_el2, x14 260 msr far_el2, x15 261 262 ldp x16, x17, [x0, #CTX_FPEXC32_EL2] 263 msr fpexc32_el2, x16 264 msr hacr_el2, x17 265 266 ldp x9, x10, [x0, #CTX_HCR_EL2] 267 msr hcr_el2, x9 268 msr hpfar_el2, x10 269 270 ldp x11, x12, [x0, #CTX_HSTR_EL2] 271 msr hstr_el2, x11 272 msr ICC_SRE_EL2, x12 273 274 ldp x13, x14, [x0, #CTX_ICH_HCR_EL2] 275 msr ICH_HCR_EL2, x13 276 msr ICH_VMCR_EL2, x14 277 278 ldp x15, x16, [x0, #CTX_MAIR_EL2] 279 msr mair_el2, x15 280 msr mdcr_el2, x16 281 282 ldp x17, x9, [x0, #CTX_PMSCR_EL2] 283 msr PMSCR_EL2, x17 284 msr sctlr_el2, x9 285 286 ldp x10, x11, [x0, #CTX_SPSR_EL2] 287 msr spsr_el2, x10 288 msr sp_el2, x11 289 290 ldp x12, x13, [x0, #CTX_TCR_EL2] 291 msr tcr_el2, x12 292 msr TRFCR_EL2, x13 293 294 ldp x14, x15, [x0, #CTX_TTBR0_EL2] 295 msr ttbr0_el2, x14 296 msr vbar_el2, x15 297 298 ldp x16, x17, [x0, #CTX_VMPIDR_EL2] 299 msr vmpidr_el2, x16 300 msr vpidr_el2, x17 301 302 ldp x9, x10, [x0, #CTX_VTCR_EL2] 303 msr vtcr_el2, x9 304 msr vttbr_el2, x10 305 306#if CTX_INCLUDE_MTE_REGS 307 ldr x11, [x0, #CTX_TFSR_EL2] 308 msr TFSR_EL2, x11 309#endif 310 311#if ENABLE_MPAM_FOR_LOWER_ELS 312 ldp x9, x10, [x0, #CTX_MPAM2_EL2] 313 msr MPAM2_EL2, x9 314 msr MPAMHCR_EL2, x10 315 316 ldp x11, x12, [x0, #CTX_MPAMVPM0_EL2] 317 msr MPAMVPM0_EL2, x11 318 msr MPAMVPM1_EL2, x12 319 320 ldp x13, x14, [x0, #CTX_MPAMVPM2_EL2] 321 msr MPAMVPM2_EL2, x13 322 msr MPAMVPM3_EL2, x14 323 324 ldp x15, x16, [x0, #CTX_MPAMVPM4_EL2] 325 msr MPAMVPM4_EL2, x15 326 msr MPAMVPM5_EL2, x16 327 328 ldp x17, x9, [x0, #CTX_MPAMVPM6_EL2] 329 msr MPAMVPM6_EL2, x17 330 msr MPAMVPM7_EL2, x9 331 332 ldr x10, [x0, #CTX_MPAMVPMV_EL2] 333 msr MPAMVPMV_EL2, x10 334#endif 335 336#if ARM_ARCH_AT_LEAST(8, 6) 337 ldp x11, x12, [x0, #CTX_HAFGRTR_EL2] 338 msr HAFGRTR_EL2, x11 339 msr HDFGRTR_EL2, x12 340 341 ldp x13, x14, [x0, #CTX_HDFGWTR_EL2] 342 msr HDFGWTR_EL2, x13 343 msr HFGITR_EL2, x14 344 345 ldp x15, x16, [x0, #CTX_HFGRTR_EL2] 346 msr HFGRTR_EL2, x15 347 msr HFGWTR_EL2, x16 348 349 ldr x17, [x0, #CTX_CNTPOFF_EL2] 350 msr CNTPOFF_EL2, x17 351#endif 352 353#if ARM_ARCH_AT_LEAST(8, 4) 354 ldp x9, x10, [x0, #CTX_CNTHPS_CTL_EL2] 355 msr cnthps_ctl_el2, x9 356 msr cnthps_cval_el2, x10 357 358 ldp x11, x12, [x0, #CTX_CNTHPS_TVAL_EL2] 359 msr cnthps_tval_el2, x11 360 msr cnthvs_ctl_el2, x12 361 362 ldp x13, x14, [x0, #CTX_CNTHVS_CVAL_EL2] 363 msr cnthvs_cval_el2, x13 364 msr cnthvs_tval_el2, x14 365 366 ldp x15, x16, [x0, #CTX_CNTHV_CTL_EL2] 367 msr cnthv_ctl_el2, x15 368 msr cnthv_cval_el2, x16 369 370 ldp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2] 371 msr cnthv_tval_el2, x17 372 msr contextidr_el2, x9 373 374 ldr x10, [x0, #CTX_SDER32_EL2] 375 msr sder32_el2, x10 376 377 ldr x11, [x0, #CTX_TTBR1_EL2] 378 msr ttbr1_el2, x11 379 380 ldr x12, [x0, #CTX_VDISR_EL2] 381 msr vdisr_el2, x12 382 383 ldr x13, [x0, #CTX_VNCR_EL2] 384 msr vncr_el2, x13 385 386 ldr x14, [x0, #CTX_VSESR_EL2] 387 msr vsesr_el2, x14 388 389 ldr x15, [x0, #CTX_VSTCR_EL2] 390 msr vstcr_el2, x15 391 392 ldr x16, [x0, #CTX_VSTTBR_EL2] 393 msr vsttbr_el2, x16 394#endif 395 396#if ARM_ARCH_AT_LEAST(8, 5) 397 ldr x17, [x0, #CTX_SCXTNUM_EL2] 398 msr scxtnum_el2, x17 399#endif 400 401 ret 402endfunc el2_sysregs_context_restore 403 404#endif /* CTX_INCLUDE_EL2_REGS */ 405 406/* ------------------------------------------------------------------ 407 * The following function strictly follows the AArch64 PCS to use 408 * x9-x17 (temporary caller-saved registers) to save EL1 system 409 * register context. It assumes that 'x0' is pointing to a 410 * 'el1_sys_regs' structure where the register context will be saved. 411 * ------------------------------------------------------------------ 412 */ 413func el1_sysregs_context_save 414 415 mrs x9, spsr_el1 416 mrs x10, elr_el1 417 stp x9, x10, [x0, #CTX_SPSR_EL1] 418 419 mrs x15, sctlr_el1 420 mrs x16, actlr_el1 421 stp x15, x16, [x0, #CTX_SCTLR_EL1] 422 423 mrs x17, cpacr_el1 424 mrs x9, csselr_el1 425 stp x17, x9, [x0, #CTX_CPACR_EL1] 426 427 mrs x10, sp_el1 428 mrs x11, esr_el1 429 stp x10, x11, [x0, #CTX_SP_EL1] 430 431 mrs x12, ttbr0_el1 432 mrs x13, ttbr1_el1 433 stp x12, x13, [x0, #CTX_TTBR0_EL1] 434 435 mrs x14, mair_el1 436 mrs x15, amair_el1 437 stp x14, x15, [x0, #CTX_MAIR_EL1] 438 439 mrs x16, tcr_el1 440 mrs x17, tpidr_el1 441 stp x16, x17, [x0, #CTX_TCR_EL1] 442 443 mrs x9, tpidr_el0 444 mrs x10, tpidrro_el0 445 stp x9, x10, [x0, #CTX_TPIDR_EL0] 446 447 mrs x13, par_el1 448 mrs x14, far_el1 449 stp x13, x14, [x0, #CTX_PAR_EL1] 450 451 mrs x15, afsr0_el1 452 mrs x16, afsr1_el1 453 stp x15, x16, [x0, #CTX_AFSR0_EL1] 454 455 mrs x17, contextidr_el1 456 mrs x9, vbar_el1 457 stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] 458 459 /* Save AArch32 system registers if the build has instructed so */ 460#if CTX_INCLUDE_AARCH32_REGS 461 mrs x11, spsr_abt 462 mrs x12, spsr_und 463 stp x11, x12, [x0, #CTX_SPSR_ABT] 464 465 mrs x13, spsr_irq 466 mrs x14, spsr_fiq 467 stp x13, x14, [x0, #CTX_SPSR_IRQ] 468 469 mrs x15, dacr32_el2 470 mrs x16, ifsr32_el2 471 stp x15, x16, [x0, #CTX_DACR32_EL2] 472#endif 473 474 /* Save NS timer registers if the build has instructed so */ 475#if NS_TIMER_SWITCH 476 mrs x10, cntp_ctl_el0 477 mrs x11, cntp_cval_el0 478 stp x10, x11, [x0, #CTX_CNTP_CTL_EL0] 479 480 mrs x12, cntv_ctl_el0 481 mrs x13, cntv_cval_el0 482 stp x12, x13, [x0, #CTX_CNTV_CTL_EL0] 483 484 mrs x14, cntkctl_el1 485 str x14, [x0, #CTX_CNTKCTL_EL1] 486#endif 487 488 /* Save MTE system registers if the build has instructed so */ 489#if CTX_INCLUDE_MTE_REGS 490 mrs x15, TFSRE0_EL1 491 mrs x16, TFSR_EL1 492 stp x15, x16, [x0, #CTX_TFSRE0_EL1] 493 494 mrs x9, RGSR_EL1 495 mrs x10, GCR_EL1 496 stp x9, x10, [x0, #CTX_RGSR_EL1] 497#endif 498 499 ret 500endfunc el1_sysregs_context_save 501 502/* ------------------------------------------------------------------ 503 * The following function strictly follows the AArch64 PCS to use 504 * x9-x17 (temporary caller-saved registers) to restore EL1 system 505 * register context. It assumes that 'x0' is pointing to a 506 * 'el1_sys_regs' structure from where the register context will be 507 * restored 508 * ------------------------------------------------------------------ 509 */ 510func el1_sysregs_context_restore 511 512 ldp x9, x10, [x0, #CTX_SPSR_EL1] 513 msr spsr_el1, x9 514 msr elr_el1, x10 515 516 ldp x15, x16, [x0, #CTX_SCTLR_EL1] 517 msr sctlr_el1, x15 518 msr actlr_el1, x16 519 520 ldp x17, x9, [x0, #CTX_CPACR_EL1] 521 msr cpacr_el1, x17 522 msr csselr_el1, x9 523 524 ldp x10, x11, [x0, #CTX_SP_EL1] 525 msr sp_el1, x10 526 msr esr_el1, x11 527 528 ldp x12, x13, [x0, #CTX_TTBR0_EL1] 529 msr ttbr0_el1, x12 530 msr ttbr1_el1, x13 531 532 ldp x14, x15, [x0, #CTX_MAIR_EL1] 533 msr mair_el1, x14 534 msr amair_el1, x15 535 536 ldp x16, x17, [x0, #CTX_TCR_EL1] 537 msr tcr_el1, x16 538 msr tpidr_el1, x17 539 540 ldp x9, x10, [x0, #CTX_TPIDR_EL0] 541 msr tpidr_el0, x9 542 msr tpidrro_el0, x10 543 544 ldp x13, x14, [x0, #CTX_PAR_EL1] 545 msr par_el1, x13 546 msr far_el1, x14 547 548 ldp x15, x16, [x0, #CTX_AFSR0_EL1] 549 msr afsr0_el1, x15 550 msr afsr1_el1, x16 551 552 ldp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] 553 msr contextidr_el1, x17 554 msr vbar_el1, x9 555 556 /* Restore AArch32 system registers if the build has instructed so */ 557#if CTX_INCLUDE_AARCH32_REGS 558 ldp x11, x12, [x0, #CTX_SPSR_ABT] 559 msr spsr_abt, x11 560 msr spsr_und, x12 561 562 ldp x13, x14, [x0, #CTX_SPSR_IRQ] 563 msr spsr_irq, x13 564 msr spsr_fiq, x14 565 566 ldp x15, x16, [x0, #CTX_DACR32_EL2] 567 msr dacr32_el2, x15 568 msr ifsr32_el2, x16 569#endif 570 /* Restore NS timer registers if the build has instructed so */ 571#if NS_TIMER_SWITCH 572 ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0] 573 msr cntp_ctl_el0, x10 574 msr cntp_cval_el0, x11 575 576 ldp x12, x13, [x0, #CTX_CNTV_CTL_EL0] 577 msr cntv_ctl_el0, x12 578 msr cntv_cval_el0, x13 579 580 ldr x14, [x0, #CTX_CNTKCTL_EL1] 581 msr cntkctl_el1, x14 582#endif 583 /* Restore MTE system registers if the build has instructed so */ 584#if CTX_INCLUDE_MTE_REGS 585 ldp x11, x12, [x0, #CTX_TFSRE0_EL1] 586 msr TFSRE0_EL1, x11 587 msr TFSR_EL1, x12 588 589 ldp x13, x14, [x0, #CTX_RGSR_EL1] 590 msr RGSR_EL1, x13 591 msr GCR_EL1, x14 592#endif 593 594 /* No explict ISB required here as ERET covers it */ 595 ret 596endfunc el1_sysregs_context_restore 597 598/* ------------------------------------------------------------------ 599 * The following function follows the aapcs_64 strictly to use 600 * x9-x17 (temporary caller-saved registers according to AArch64 PCS) 601 * to save floating point register context. It assumes that 'x0' is 602 * pointing to a 'fp_regs' structure where the register context will 603 * be saved. 604 * 605 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 606 * However currently we don't use VFP registers nor set traps in 607 * Trusted Firmware, and assume it's cleared. 608 * 609 * TODO: Revisit when VFP is used in secure world 610 * ------------------------------------------------------------------ 611 */ 612#if CTX_INCLUDE_FPREGS 613func fpregs_context_save 614 stp q0, q1, [x0, #CTX_FP_Q0] 615 stp q2, q3, [x0, #CTX_FP_Q2] 616 stp q4, q5, [x0, #CTX_FP_Q4] 617 stp q6, q7, [x0, #CTX_FP_Q6] 618 stp q8, q9, [x0, #CTX_FP_Q8] 619 stp q10, q11, [x0, #CTX_FP_Q10] 620 stp q12, q13, [x0, #CTX_FP_Q12] 621 stp q14, q15, [x0, #CTX_FP_Q14] 622 stp q16, q17, [x0, #CTX_FP_Q16] 623 stp q18, q19, [x0, #CTX_FP_Q18] 624 stp q20, q21, [x0, #CTX_FP_Q20] 625 stp q22, q23, [x0, #CTX_FP_Q22] 626 stp q24, q25, [x0, #CTX_FP_Q24] 627 stp q26, q27, [x0, #CTX_FP_Q26] 628 stp q28, q29, [x0, #CTX_FP_Q28] 629 stp q30, q31, [x0, #CTX_FP_Q30] 630 631 mrs x9, fpsr 632 str x9, [x0, #CTX_FP_FPSR] 633 634 mrs x10, fpcr 635 str x10, [x0, #CTX_FP_FPCR] 636 637#if CTX_INCLUDE_AARCH32_REGS 638 mrs x11, fpexc32_el2 639 str x11, [x0, #CTX_FP_FPEXC32_EL2] 640#endif 641 ret 642endfunc fpregs_context_save 643 644/* ------------------------------------------------------------------ 645 * The following function follows the aapcs_64 strictly to use x9-x17 646 * (temporary caller-saved registers according to AArch64 PCS) to 647 * restore floating point register context. It assumes that 'x0' is 648 * pointing to a 'fp_regs' structure from where the register context 649 * will be restored. 650 * 651 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 652 * However currently we don't use VFP registers nor set traps in 653 * Trusted Firmware, and assume it's cleared. 654 * 655 * TODO: Revisit when VFP is used in secure world 656 * ------------------------------------------------------------------ 657 */ 658func fpregs_context_restore 659 ldp q0, q1, [x0, #CTX_FP_Q0] 660 ldp q2, q3, [x0, #CTX_FP_Q2] 661 ldp q4, q5, [x0, #CTX_FP_Q4] 662 ldp q6, q7, [x0, #CTX_FP_Q6] 663 ldp q8, q9, [x0, #CTX_FP_Q8] 664 ldp q10, q11, [x0, #CTX_FP_Q10] 665 ldp q12, q13, [x0, #CTX_FP_Q12] 666 ldp q14, q15, [x0, #CTX_FP_Q14] 667 ldp q16, q17, [x0, #CTX_FP_Q16] 668 ldp q18, q19, [x0, #CTX_FP_Q18] 669 ldp q20, q21, [x0, #CTX_FP_Q20] 670 ldp q22, q23, [x0, #CTX_FP_Q22] 671 ldp q24, q25, [x0, #CTX_FP_Q24] 672 ldp q26, q27, [x0, #CTX_FP_Q26] 673 ldp q28, q29, [x0, #CTX_FP_Q28] 674 ldp q30, q31, [x0, #CTX_FP_Q30] 675 676 ldr x9, [x0, #CTX_FP_FPSR] 677 msr fpsr, x9 678 679 ldr x10, [x0, #CTX_FP_FPCR] 680 msr fpcr, x10 681 682#if CTX_INCLUDE_AARCH32_REGS 683 ldr x11, [x0, #CTX_FP_FPEXC32_EL2] 684 msr fpexc32_el2, x11 685#endif 686 /* 687 * No explict ISB required here as ERET to 688 * switch to secure EL1 or non-secure world 689 * covers it 690 */ 691 692 ret 693endfunc fpregs_context_restore 694#endif /* CTX_INCLUDE_FPREGS */ 695 696/* ------------------------------------------------------------------ 697 * The following function is used to save and restore all the general 698 * purpose and ARMv8.3-PAuth (if enabled) registers. 699 * It also checks if Secure Cycle Counter is not disabled in MDCR_EL3 700 * when ARMv8.5-PMU is implemented, and if called from Non-secure 701 * state saves PMCR_EL0 and disables Cycle Counter. 702 * 703 * Ideally we would only save and restore the callee saved registers 704 * when a world switch occurs but that type of implementation is more 705 * complex. So currently we will always save and restore these 706 * registers on entry and exit of EL3. 707 * These are not macros to ensure their invocation fits within the 32 708 * instructions per exception vector. 709 * clobbers: x18 710 * ------------------------------------------------------------------ 711 */ 712func save_gp_pmcr_pauth_regs 713 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 714 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 715 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 716 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 717 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 718 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 719 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 720 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 721 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 722 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 723 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 724 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 725 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 726 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 727 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 728 mrs x18, sp_el0 729 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 730 731 /* ---------------------------------------------------------- 732 * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, 733 * meaning that ARMv8-PMU is not implemented and PMCR_EL0 734 * should be saved in non-secure context. 735 * ---------------------------------------------------------- 736 */ 737 mrs x9, mdcr_el3 738 tst x9, #MDCR_SCCD_BIT 739 bne 1f 740 741 /* Secure Cycle Counter is not disabled */ 742 mrs x9, pmcr_el0 743 744 /* Check caller's security state */ 745 mrs x10, scr_el3 746 tst x10, #SCR_NS_BIT 747 beq 2f 748 749 /* Save PMCR_EL0 if called from Non-secure state */ 750 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 751 752 /* Disable cycle counter when event counting is prohibited */ 7532: orr x9, x9, #PMCR_EL0_DP_BIT 754 msr pmcr_el0, x9 755 isb 7561: 757#if CTX_INCLUDE_PAUTH_REGS 758 /* ---------------------------------------------------------- 759 * Save the ARMv8.3-PAuth keys as they are not banked 760 * by exception level 761 * ---------------------------------------------------------- 762 */ 763 add x19, sp, #CTX_PAUTH_REGS_OFFSET 764 765 mrs x20, APIAKeyLo_EL1 /* x21:x20 = APIAKey */ 766 mrs x21, APIAKeyHi_EL1 767 mrs x22, APIBKeyLo_EL1 /* x23:x22 = APIBKey */ 768 mrs x23, APIBKeyHi_EL1 769 mrs x24, APDAKeyLo_EL1 /* x25:x24 = APDAKey */ 770 mrs x25, APDAKeyHi_EL1 771 mrs x26, APDBKeyLo_EL1 /* x27:x26 = APDBKey */ 772 mrs x27, APDBKeyHi_EL1 773 mrs x28, APGAKeyLo_EL1 /* x29:x28 = APGAKey */ 774 mrs x29, APGAKeyHi_EL1 775 776 stp x20, x21, [x19, #CTX_PACIAKEY_LO] 777 stp x22, x23, [x19, #CTX_PACIBKEY_LO] 778 stp x24, x25, [x19, #CTX_PACDAKEY_LO] 779 stp x26, x27, [x19, #CTX_PACDBKEY_LO] 780 stp x28, x29, [x19, #CTX_PACGAKEY_LO] 781#endif /* CTX_INCLUDE_PAUTH_REGS */ 782 783 ret 784endfunc save_gp_pmcr_pauth_regs 785 786/* ------------------------------------------------------------------ 787 * This function restores ARMv8.3-PAuth (if enabled) and all general 788 * purpose registers except x30 from the CPU context. 789 * x30 register must be explicitly restored by the caller. 790 * ------------------------------------------------------------------ 791 */ 792func restore_gp_pmcr_pauth_regs 793#if CTX_INCLUDE_PAUTH_REGS 794 /* Restore the ARMv8.3 PAuth keys */ 795 add x10, sp, #CTX_PAUTH_REGS_OFFSET 796 797 ldp x0, x1, [x10, #CTX_PACIAKEY_LO] /* x1:x0 = APIAKey */ 798 ldp x2, x3, [x10, #CTX_PACIBKEY_LO] /* x3:x2 = APIBKey */ 799 ldp x4, x5, [x10, #CTX_PACDAKEY_LO] /* x5:x4 = APDAKey */ 800 ldp x6, x7, [x10, #CTX_PACDBKEY_LO] /* x7:x6 = APDBKey */ 801 ldp x8, x9, [x10, #CTX_PACGAKEY_LO] /* x9:x8 = APGAKey */ 802 803 msr APIAKeyLo_EL1, x0 804 msr APIAKeyHi_EL1, x1 805 msr APIBKeyLo_EL1, x2 806 msr APIBKeyHi_EL1, x3 807 msr APDAKeyLo_EL1, x4 808 msr APDAKeyHi_EL1, x5 809 msr APDBKeyLo_EL1, x6 810 msr APDBKeyHi_EL1, x7 811 msr APGAKeyLo_EL1, x8 812 msr APGAKeyHi_EL1, x9 813#endif /* CTX_INCLUDE_PAUTH_REGS */ 814 815 /* ---------------------------------------------------------- 816 * Restore PMCR_EL0 when returning to Non-secure state if 817 * Secure Cycle Counter is not disabled in MDCR_EL3 when 818 * ARMv8.5-PMU is implemented. 819 * ---------------------------------------------------------- 820 */ 821 mrs x0, scr_el3 822 tst x0, #SCR_NS_BIT 823 beq 2f 824 825 /* ---------------------------------------------------------- 826 * Back to Non-secure state. 827 * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, 828 * meaning that ARMv8-PMU is not implemented and PMCR_EL0 829 * should be restored from non-secure context. 830 * ---------------------------------------------------------- 831 */ 832 mrs x0, mdcr_el3 833 tst x0, #MDCR_SCCD_BIT 834 bne 2f 835 ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 836 msr pmcr_el0, x0 8372: 838 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 839 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 840 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 841 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 842 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 843 ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 844 ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 845 ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 846 ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 847 ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 848 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 849 ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 850 ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 851 ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 852 ldr x28, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 853 msr sp_el0, x28 854 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 855 ret 856endfunc restore_gp_pmcr_pauth_regs 857 858/* ------------------------------------------------------------------ 859 * This routine assumes that the SP_EL3 is pointing to a valid 860 * context structure from where the gp regs and other special 861 * registers can be retrieved. 862 * ------------------------------------------------------------------ 863 */ 864func el3_exit 865#if ENABLE_ASSERTIONS 866 /* el3_exit assumes SP_EL0 on entry */ 867 mrs x17, spsel 868 cmp x17, #MODE_SP_EL0 869 ASM_ASSERT(eq) 870#endif 871 872 /* ---------------------------------------------------------- 873 * Save the current SP_EL0 i.e. the EL3 runtime stack which 874 * will be used for handling the next SMC. 875 * Then switch to SP_EL3. 876 * ---------------------------------------------------------- 877 */ 878 mov x17, sp 879 msr spsel, #MODE_SP_ELX 880 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 881 882 /* ---------------------------------------------------------- 883 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET 884 * ---------------------------------------------------------- 885 */ 886 ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 887 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 888 msr scr_el3, x18 889 msr spsr_el3, x16 890 msr elr_el3, x17 891 892#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 893 /* ---------------------------------------------------------- 894 * Restore mitigation state as it was on entry to EL3 895 * ---------------------------------------------------------- 896 */ 897 ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE] 898 cbz x17, 1f 899 blr x17 9001: 901#endif 902 /* ---------------------------------------------------------- 903 * Restore general purpose (including x30), PMCR_EL0 and 904 * ARMv8.3-PAuth registers. 905 * Exit EL3 via ERET to a lower exception level. 906 * ---------------------------------------------------------- 907 */ 908 bl restore_gp_pmcr_pauth_regs 909 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 910 911#if IMAGE_BL31 && RAS_EXTENSION 912 /* ---------------------------------------------------------- 913 * Issue Error Synchronization Barrier to synchronize SErrors 914 * before exiting EL3. We're running with EAs unmasked, so 915 * any synchronized errors would be taken immediately; 916 * therefore no need to inspect DISR_EL1 register. 917 * ---------------------------------------------------------- 918 */ 919 esb 920#endif 921 exception_return 922 923endfunc el3_exit 924