1/* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/bl_common.ld.h> 8#include <lib/xlat_tables/xlat_tables_defs.h> 9 10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12ENTRY(bl1_entrypoint) 13 14MEMORY { 15 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE 16 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE 17} 18 19SECTIONS 20{ 21 . = BL1_RO_BASE; 22 ASSERT(. == ALIGN(PAGE_SIZE), 23 "BL1_RO_BASE address is not aligned on a page boundary.") 24 25#if SEPARATE_CODE_AND_RODATA 26 .text . : { 27 __TEXT_START__ = .; 28 *bl1_entrypoint.o(.text*) 29 *(SORT_BY_ALIGNMENT(.text*)) 30 *(.vectors) 31 . = ALIGN(PAGE_SIZE); 32 __TEXT_END__ = .; 33 } >ROM 34 35 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 36 .ARM.extab . : { 37 *(.ARM.extab* .gnu.linkonce.armextab.*) 38 } >ROM 39 40 .ARM.exidx . : { 41 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 42 } >ROM 43 44 .rodata . : { 45 __RODATA_START__ = .; 46 *(SORT_BY_ALIGNMENT(.rodata*)) 47 48 RODATA_COMMON 49 50 /* 51 * No need to pad out the .rodata section to a page boundary. Next is 52 * the .data section, which can mapped in ROM with the same memory 53 * attributes as the .rodata section. 54 * 55 * Pad out to 16 bytes though as .data section needs to be 16 byte 56 * aligned and lld does not align the LMA to the aligment specified 57 * on the .data section. 58 */ 59 __RODATA_END__ = .; 60 . = ALIGN(16); 61 } >ROM 62#else 63 ro . : { 64 __RO_START__ = .; 65 *bl1_entrypoint.o(.text*) 66 *(SORT_BY_ALIGNMENT(.text*)) 67 *(SORT_BY_ALIGNMENT(.rodata*)) 68 69 RODATA_COMMON 70 71 *(.vectors) 72 __RO_END__ = .; 73 74 /* 75 * Pad out to 16 bytes as .data section needs to be 16 byte aligned and 76 * lld does not align the LMA to the aligment specified on the .data 77 * section. 78 */ 79 . = ALIGN(16); 80 } >ROM 81#endif 82 83 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 84 "cpu_ops not defined for this platform.") 85 86 . = BL1_RW_BASE; 87 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE), 88 "BL1_RW_BASE address is not aligned on a page boundary.") 89 90 /* 91 * The .data section gets copied from ROM to RAM at runtime. 92 * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes 93 * aligned regions in it. 94 * Its VMA must be page-aligned as it marks the first read/write page. 95 * 96 * It must be placed at a lower address than the stacks if the stack 97 * protector is enabled. Alternatively, the .data.stack_protector_canary 98 * section can be placed independently of the main .data section. 99 */ 100 .data . : ALIGN(16) { 101 __DATA_RAM_START__ = .; 102 *(SORT_BY_ALIGNMENT(.data*)) 103 __DATA_RAM_END__ = .; 104 } >RAM AT>ROM 105 106 STACK_SECTION >RAM 107 BSS_SECTION >RAM 108 XLAT_TABLE_SECTION >RAM 109 110#if USE_COHERENT_MEM 111 /* 112 * The base address of the coherent memory section must be page-aligned (4K) 113 * to guarantee that the coherent data are stored on their own pages and 114 * are not mixed with normal data. This is required to set up the correct 115 * memory attributes for the coherent data page tables. 116 */ 117 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 118 __COHERENT_RAM_START__ = .; 119 *(tzfw_coherent_mem) 120 __COHERENT_RAM_END_UNALIGNED__ = .; 121 /* 122 * Memory page(s) mapped to this section will be marked 123 * as device memory. No other unexpected data must creep in. 124 * Ensure the rest of the current memory page is unused. 125 */ 126 . = ALIGN(PAGE_SIZE); 127 __COHERENT_RAM_END__ = .; 128 } >RAM 129#endif 130 131 __BL1_RAM_START__ = ADDR(.data); 132 __BL1_RAM_END__ = .; 133 134 __DATA_ROM_START__ = LOADADDR(.data); 135 __DATA_SIZE__ = SIZEOF(.data); 136 137 /* 138 * The .data section is the last PROGBITS section so its end marks the end 139 * of BL1's actual content in Trusted ROM. 140 */ 141 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 142 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, 143 "BL1's ROM content has exceeded its limit.") 144 145 __BSS_SIZE__ = SIZEOF(.bss); 146 147#if USE_COHERENT_MEM 148 __COHERENT_RAM_UNALIGNED_SIZE__ = 149 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 150#endif 151 152 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") 153} 154