1/* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/bl_common.ld.h> 8#include <lib/xlat_tables/xlat_tables_defs.h> 9 10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12ENTRY(bl2_entrypoint) 13 14MEMORY { 15#if BL2_IN_XIP_MEM 16 ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE 17 RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE 18#else 19 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE 20#endif 21} 22 23#if !BL2_IN_XIP_MEM 24#define ROM RAM 25#endif 26 27SECTIONS 28{ 29#if BL2_IN_XIP_MEM 30 . = BL2_RO_BASE; 31 ASSERT(. == ALIGN(PAGE_SIZE), 32 "BL2_RO_BASE address is not aligned on a page boundary.") 33#else 34 . = BL2_BASE; 35 ASSERT(. == ALIGN(PAGE_SIZE), 36 "BL2_BASE address is not aligned on a page boundary.") 37#endif 38 39#if SEPARATE_CODE_AND_RODATA 40 .text . : { 41 __TEXT_START__ = .; 42 __TEXT_RESIDENT_START__ = .; 43 *bl2_el3_entrypoint.o(.text*) 44 *(.text.asm.*) 45 __TEXT_RESIDENT_END__ = .; 46 *(SORT_BY_ALIGNMENT(.text*)) 47 *(.vectors) 48 . = ALIGN(PAGE_SIZE); 49 __TEXT_END__ = .; 50 } >ROM 51 52 .rodata . : { 53 __RODATA_START__ = .; 54 *(SORT_BY_ALIGNMENT(.rodata*)) 55 56 PARSER_LIB_DESCS 57 CPU_OPS 58 GOT 59 60 . = ALIGN(PAGE_SIZE); 61 __RODATA_END__ = .; 62 } >ROM 63 64 ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE, 65 "Resident part of BL2 has exceeded its limit.") 66#else 67 ro . : { 68 __RO_START__ = .; 69 __TEXT_RESIDENT_START__ = .; 70 *bl2_el3_entrypoint.o(.text*) 71 *(.text.asm.*) 72 __TEXT_RESIDENT_END__ = .; 73 *(SORT_BY_ALIGNMENT(.text*)) 74 *(SORT_BY_ALIGNMENT(.rodata*)) 75 76 CPU_OPS 77 PARSER_LIB_DESCS 78 GOT 79 80 *(.vectors) 81 __RO_END_UNALIGNED__ = .; 82 /* 83 * Memory page(s) mapped to this section will be marked as 84 * read-only, executable. No RW data from the next section must 85 * creep in. Ensure the rest of the current memory page is unused. 86 */ 87 . = ALIGN(PAGE_SIZE); 88 89 __RO_END__ = .; 90 } >ROM 91#endif 92 93 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 94 "cpu_ops not defined for this platform.") 95 96#if BL2_IN_XIP_MEM 97 . = BL2_RW_BASE; 98 ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE), 99 "BL2_RW_BASE address is not aligned on a page boundary.") 100#endif 101 102 /* 103 * Define a linker symbol to mark start of the RW memory area for this 104 * image. 105 */ 106 __RW_START__ = . ; 107 108 /* 109 * .data must be placed at a lower address than the stacks if the stack 110 * protector is enabled. Alternatively, the .data.stack_protector_canary 111 * section can be placed independently of the main .data section. 112 */ 113 .data . : { 114 __DATA_RAM_START__ = .; 115 *(SORT_BY_ALIGNMENT(.data*)) 116 __DATA_RAM_END__ = .; 117 } >RAM AT>ROM 118 119 /* 120 * .rela.dyn needs to come after .data for the read-elf utility to parse 121 * this section correctly. Ensure 8-byte alignment so that the fields of 122 * RELA data structure are aligned. 123 */ 124 . = ALIGN(8); 125 __RELA_START__ = .; 126 .rela.dyn . : { 127 } >RAM 128 __RELA_END__ = .; 129 130 stacks (NOLOAD) : { 131 __STACKS_START__ = .; 132 *(tzfw_normal_stacks) 133 __STACKS_END__ = .; 134 } >RAM 135 136 /* 137 * The .bss section gets initialised to 0 at runtime. 138 * Its base address should be 16-byte aligned for better performance of the 139 * zero-initialization code. 140 */ 141 .bss : ALIGN(16) { 142 __BSS_START__ = .; 143 *(SORT_BY_ALIGNMENT(.bss*)) 144 *(COMMON) 145 __BSS_END__ = .; 146 } >RAM 147 148 XLAT_TABLE_SECTION >RAM 149 150#if USE_COHERENT_MEM 151 /* 152 * The base address of the coherent memory section must be page-aligned (4K) 153 * to guarantee that the coherent data are stored on their own pages and 154 * are not mixed with normal data. This is required to set up the correct 155 * memory attributes for the coherent data page tables. 156 */ 157 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 158 __COHERENT_RAM_START__ = .; 159 *(tzfw_coherent_mem) 160 __COHERENT_RAM_END_UNALIGNED__ = .; 161 /* 162 * Memory page(s) mapped to this section will be marked 163 * as device memory. No other unexpected data must creep in. 164 * Ensure the rest of the current memory page is unused. 165 */ 166 . = ALIGN(PAGE_SIZE); 167 __COHERENT_RAM_END__ = .; 168 } >RAM 169#endif 170 171 /* 172 * Define a linker symbol to mark end of the RW memory area for this 173 * image. 174 */ 175 __RW_END__ = .; 176 __BL2_END__ = .; 177 178 /DISCARD/ : { 179 *(.dynsym .dynstr .hash .gnu.hash) 180 } 181 182#if BL2_IN_XIP_MEM 183 __BL2_RAM_START__ = ADDR(.data); 184 __BL2_RAM_END__ = .; 185 186 __DATA_ROM_START__ = LOADADDR(.data); 187 __DATA_SIZE__ = SIZEOF(.data); 188 189 /* 190 * The .data section is the last PROGBITS section so its end marks the end 191 * of BL2's RO content in XIP memory.. 192 */ 193 __BL2_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 194 ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT, 195 "BL2's RO content has exceeded its limit.") 196#endif 197 __BSS_SIZE__ = SIZEOF(.bss); 198 199 200#if USE_COHERENT_MEM 201 __COHERENT_RAM_UNALIGNED_SIZE__ = 202 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 203#endif 204 205#if BL2_IN_XIP_MEM 206 ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.") 207#else 208 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") 209#endif 210} 211