1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <arch_helpers.h> 11 #include <bl31/bl31.h> 12 #include <bl31/interrupt_mgmt.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/ep_info.h> 16 #include <common/interrupt_props.h> 17 #include <context.h> 18 #include <cortex_a57.h> 19 #include <denver.h> 20 #include <drivers/arm/gic_common.h> 21 #include <drivers/arm/gicv2.h> 22 #include <drivers/console.h> 23 #include <lib/el3_runtime/context_mgmt.h> 24 #include <lib/utils.h> 25 #include <lib/xlat_tables/xlat_tables_v2.h> 26 #include <plat/common/platform.h> 27 28 #include <mce.h> 29 #include <tegra_def.h> 30 #include <tegra_platform.h> 31 #include <tegra_private.h> 32 33 extern void memcpy16(void *dest, const void *src, unsigned int length); 34 35 /******************************************************************************* 36 * Tegra186 CPU numbers in cluster #0 37 ******************************************************************************* 38 */ 39 #define TEGRA186_CLUSTER0_CORE2 2U 40 #define TEGRA186_CLUSTER0_CORE3 3U 41 42 /******************************************************************************* 43 * The Tegra power domain tree has a single system level power domain i.e. a 44 * single root node. The first entry in the power domain descriptor specifies 45 * the number of power domains at the highest power level. 46 ******************************************************************************* 47 */ 48 static const uint8_t tegra_power_domain_tree_desc[] = { 49 /* No of root nodes */ 50 1, 51 /* No of clusters */ 52 PLATFORM_CLUSTER_COUNT, 53 /* No of CPU cores - cluster0 */ 54 PLATFORM_MAX_CPUS_PER_CLUSTER, 55 /* No of CPU cores - cluster1 */ 56 PLATFORM_MAX_CPUS_PER_CLUSTER 57 }; 58 59 /******************************************************************************* 60 * This function returns the Tegra default topology tree information. 61 ******************************************************************************/ 62 const uint8_t *plat_get_power_domain_tree_desc(void) 63 { 64 return tegra_power_domain_tree_desc; 65 } 66 67 /* 68 * Table of regions to map using the MMU. 69 */ 70 static const mmap_region_t tegra_mmap[] = { 71 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */ 72 MT_DEVICE | MT_RW | MT_SECURE), 73 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ 74 MT_DEVICE | MT_RW | MT_SECURE), 75 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */ 76 MT_DEVICE | MT_RW | MT_SECURE), 77 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */ 78 MT_DEVICE | MT_RW | MT_SECURE), 79 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ 80 MT_DEVICE | MT_RW | MT_SECURE), 81 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ 82 MT_DEVICE | MT_RW | MT_SECURE), 83 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ 84 MT_DEVICE | MT_RW | MT_SECURE), 85 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */ 86 MT_DEVICE | MT_RW | MT_SECURE), 87 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */ 88 MT_DEVICE | MT_RW | MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */ 90 MT_DEVICE | MT_RW | MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */ 92 MT_DEVICE | MT_RW | MT_SECURE), 93 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */ 94 MT_DEVICE | MT_RW | MT_SECURE), 95 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ 96 MT_DEVICE | MT_RW | MT_SECURE), 97 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ 98 MT_DEVICE | MT_RW | MT_SECURE), 99 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000U, /* 4KB */ 100 MT_DEVICE | MT_RO | MT_SECURE), 101 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */ 102 MT_DEVICE | MT_RW | MT_SECURE), 103 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */ 104 MT_DEVICE | MT_RW | MT_SECURE), 105 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000U, /* 128KB - ARM/Denver */ 106 MT_DEVICE | MT_RW | MT_SECURE), 107 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */ 108 MT_DEVICE | MT_RW | MT_SECURE), 109 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x10000U, /* 64KB */ 110 MT_DEVICE | MT_RW | MT_SECURE), 111 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, TEGRA_BPMP_IPC_CH_MAP_SIZE, /* 4KB */ 112 MT_DEVICE | MT_RW | MT_SECURE), 113 MAP_REGION_FLAT(TEGRA_BPMP_IPC_RX_PHYS_BASE, TEGRA_BPMP_IPC_CH_MAP_SIZE, /* 4KB */ 114 MT_DEVICE | MT_RW | MT_SECURE), 115 {0} 116 }; 117 118 /******************************************************************************* 119 * Set up the pagetables as per the platform memory map & initialize the MMU 120 ******************************************************************************/ 121 const mmap_region_t *plat_get_mmio_map(void) 122 { 123 /* MMIO space */ 124 return tegra_mmap; 125 } 126 127 /******************************************************************************* 128 * Handler to get the System Counter Frequency 129 ******************************************************************************/ 130 uint32_t plat_get_syscnt_freq2(void) 131 { 132 return 31250000; 133 } 134 135 /******************************************************************************* 136 * Maximum supported UART controllers 137 ******************************************************************************/ 138 #define TEGRA186_MAX_UART_PORTS 7 139 140 /******************************************************************************* 141 * This variable holds the UART port base addresses 142 ******************************************************************************/ 143 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 144 0, /* undefined - treated as an error case */ 145 TEGRA_UARTA_BASE, 146 TEGRA_UARTB_BASE, 147 TEGRA_UARTC_BASE, 148 TEGRA_UARTD_BASE, 149 TEGRA_UARTE_BASE, 150 TEGRA_UARTF_BASE, 151 TEGRA_UARTG_BASE, 152 }; 153 154 /******************************************************************************* 155 * Enable console corresponding to the console ID 156 ******************************************************************************/ 157 void plat_enable_console(int32_t id) 158 { 159 static console_t uart_console; 160 uint32_t console_clock; 161 162 if ((id > 0) && (id < TEGRA186_MAX_UART_PORTS)) { 163 /* 164 * Reference clock used by the FPGAs is a lot slower. 165 */ 166 if (tegra_platform_is_fpga()) { 167 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; 168 } else { 169 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; 170 } 171 172 (void)console_16550_register(tegra186_uart_addresses[id], 173 console_clock, 174 TEGRA_CONSOLE_BAUDRATE, 175 &uart_console); 176 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT | 177 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 178 } 179 } 180 181 /******************************************************************************* 182 * Handler for early platform setup 183 ******************************************************************************/ 184 void plat_early_platform_setup(void) 185 { 186 uint64_t impl, val; 187 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 188 189 /* sanity check MCE firmware compatibility */ 190 mce_verify_firmware_version(); 191 192 impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; 193 194 /* 195 * Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186 196 * A02p and beyond). 197 */ 198 if ((plat_params->l2_ecc_parity_prot_dis != 1) && 199 (impl != (uint64_t)DENVER_IMPL)) { 200 201 val = read_l2ctlr_el1(); 202 val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 203 write_l2ctlr_el1(val); 204 } 205 } 206 207 /******************************************************************************* 208 * Handler for late platform setup 209 ******************************************************************************/ 210 void plat_late_platform_setup(void) 211 { 212 ; /* do nothing */ 213 } 214 215 /* Secure IRQs for Tegra186 */ 216 static const interrupt_prop_t tegra186_interrupt_props[] = { 217 INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 218 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 219 INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 220 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 221 }; 222 223 /******************************************************************************* 224 * Initialize the GIC and SGIs 225 ******************************************************************************/ 226 void plat_gic_setup(void) 227 { 228 tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props)); 229 tegra_gic_init(); 230 231 /* 232 * Initialize the FIQ handler only if the platform supports any 233 * FIQ interrupt sources. 234 */ 235 tegra_fiq_handler_setup(); 236 } 237 238 /******************************************************************************* 239 * Return pointer to the BL31 params from previous bootloader 240 ******************************************************************************/ 241 struct tegra_bl31_params *plat_get_bl31_params(void) 242 { 243 uint32_t val; 244 245 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR); 246 247 return (struct tegra_bl31_params *)(uintptr_t)val; 248 } 249 250 /******************************************************************************* 251 * Return pointer to the BL31 platform params from previous bootloader 252 ******************************************************************************/ 253 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 254 { 255 uint32_t val; 256 257 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR); 258 259 return (plat_params_from_bl2_t *)(uintptr_t)val; 260 } 261 262 /******************************************************************************* 263 * This function implements a part of the critical interface between the psci 264 * generic layer and the platform that allows the former to query the platform 265 * to convert an MPIDR to a unique linear index. An error code (-1) is returned 266 * in case the MPIDR is invalid. 267 ******************************************************************************/ 268 int32_t plat_core_pos_by_mpidr(u_register_t mpidr) 269 { 270 u_register_t cluster_id, cpu_id, pos; 271 int32_t ret; 272 273 cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK; 274 cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK; 275 276 /* 277 * Validate cluster_id by checking whether it represents 278 * one of the two clusters present on the platform. 279 * Validate cpu_id by checking whether it represents a CPU in 280 * one of the two clusters present on the platform. 281 */ 282 if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) || 283 (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) { 284 ret = PSCI_E_NOT_PRESENT; 285 } else { 286 /* calculate the core position */ 287 pos = cpu_id + (cluster_id << 2U); 288 289 /* check for non-existent CPUs */ 290 if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) { 291 ret = PSCI_E_NOT_PRESENT; 292 } else { 293 ret = (int32_t)pos; 294 } 295 } 296 297 return ret; 298 } 299 300 /******************************************************************************* 301 * Handler to relocate BL32 image to TZDRAM 302 ******************************************************************************/ 303 void plat_relocate_bl32_image(const image_info_t *bl32_img_info) 304 { 305 const plat_params_from_bl2_t *plat_bl31_params = plat_get_bl31_plat_params(); 306 const entry_point_info_t *bl32_ep_info = bl31_plat_get_next_image_ep_info(SECURE); 307 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 308 309 if ((bl32_img_info != NULL) && (bl32_ep_info != NULL)) { 310 311 /* Relocate BL32 if it resides outside of the TZDRAM */ 312 tzdram_start = plat_bl31_params->tzdram_base; 313 tzdram_end = plat_bl31_params->tzdram_base + 314 plat_bl31_params->tzdram_size; 315 bl32_start = bl32_img_info->image_base; 316 bl32_end = bl32_img_info->image_base + bl32_img_info->image_size; 317 318 assert(tzdram_end > tzdram_start); 319 assert(bl32_end > bl32_start); 320 assert(bl32_ep_info->pc > tzdram_start); 321 assert(bl32_ep_info->pc < tzdram_end); 322 323 /* relocate BL32 */ 324 if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) { 325 326 INFO("Relocate BL32 to TZDRAM\n"); 327 328 (void)memcpy16((void *)(uintptr_t)bl32_ep_info->pc, 329 (void *)(uintptr_t)bl32_start, 330 bl32_img_info->image_size); 331 332 /* clean up non-secure intermediate buffer */ 333 zeromem((void *)(uintptr_t)bl32_start, 334 bl32_img_info->image_size); 335 } 336 } 337 } 338 339 /******************************************************************************* 340 * Handler to indicate support for System Suspend 341 ******************************************************************************/ 342 bool plat_supports_system_suspend(void) 343 { 344 return true; 345 } 346