feat(intel): add support for query SDM config error and status

Currently the FPGA reconfig status only return a single error status
which make the debugging of FPGA reconfiguration hard.

This patch

feat(intel): add support for query SDM config error and status

Currently the FPGA reconfig status only return a single error status
which make the debugging of FPGA reconfiguration hard.

This patch is to expose the error status, major error code and
minor error code, for the FPGA reconfig to upper layer app.

Change-Id: I2fc68e30b45ff137f3e52f9569fdf2eaf2ca94ee
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): add FPGA isolation trigger when reconfiguration

This change is to add in new Mailbox CMD to SDM for MPFE isolation.

Change-Id: I52c84dc227e1c8edbded63c699ded63e431d9af2
Signed-off-by: S

fix(intel): add FPGA isolation trigger when reconfiguration

This change is to add in new Mailbox CMD to SDM for MPFE isolation.

Change-Id: I52c84dc227e1c8edbded63c699ded63e431d9af2
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): redesign F2SOC bridge enable and disable flow for Agilex5

This is to redesign the flow of F2SOC bridge enable and disable.

Change-Id: I9b2a2a11fa2ad8e622765971fdf59a0738246e13
Signed-of

fix(intel): redesign F2SOC bridge enable and disable flow for Agilex5

This is to redesign the flow of F2SOC bridge enable and disable.

Change-Id: I9b2a2a11fa2ad8e622765971fdf59a0738246e13
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): add in JTAG ID for Linux FCS" into integration

Merge "feat(intel): add build option for boot source" into integration

Merge "fix(intel): refactor SDMMC driver for Altera products" into integration

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
S

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update Agilex5 warm reset subroutines

Update the 'plat_get_my_entrypoint' assembly routine to
differentiate between cold reset, warm reset and SMP
secondary boot cores request.
Add secon

fix(intel): update Agilex5 warm reset subroutines

Update the 'plat_get_my_entrypoint' assembly routine to
differentiate between cold reset, warm reset and SMP
secondary boot cores request.
Add secondary core boot request markup in BL31.
Perform CACHE flush/clean ops in case of warm reset request also.

Change-Id: I7d33e362a3a513c60c8333e062ce832aa7facf38
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): add in JTAG ID for Linux FCS

This is for SMMU and Remapper enabled/disabled for
Linux FCS feature. The JTAG ID is to determine which
Agilex5 model shall be implemented.

Change-Id: Ib10d

fix(intel): add in JTAG ID for Linux FCS

This is for SMMU and Remapper enabled/disabled for
Linux FCS feature. The JTAG ID is to determine which
Agilex5 model shall be implemented.

Change-Id: Ib10d0062de8f6e27413af3dd271d97b9c2e5c079
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): add build option for boot source

Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update n

feat(intel): add build option for boot source

Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update needed when
need to change boot source.

Also, it will have ARM_LINUX_KERNEL_AS_BL33 flag for each
platform in platform.mk. This will be easily to control
based on platform build.

Change-Id: I383beb8cbca5ec0f247221ad42796554adc3daae
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update all the platforms hand-off data offset value

Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Ic

fix(intel): update all the platforms hand-off data offset value

Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Icfe917f788814c329659c44e298cf05d6e3d0dd9
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): fix CCU for cache maintenance" into integration

Merge "fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset" into integration

fix(intel): fix CCU for cache maintenance

Fix CCU settings for cache maintenance.

Change-Id: I9af35a6ab7aa9ee20e05ba82d0a042948ac29a93
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-

fix(intel): fix CCU for cache maintenance

Fix CCU settings for cache maintenance.

Change-Id: I9af35a6ab7aa9ee20e05ba82d0a042948ac29a93
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): update preloaded_bl33_base for legacy product

Update preloaded_bl33_base for legacy product for Yocto.

The Yocto Jenkins build was initially configured to build products
where the start

fix(intel): update preloaded_bl33_base for legacy product

Update preloaded_bl33_base for legacy product for Yocto.

The Yocto Jenkins build was initially configured to build products
where the starting of the DDR is from 0x0000 0000. And if there is
no NS_image_offset set, the Jenkins is not able to acquire the correct
address offset to boot up the system. However, in the direct OS boot,
there is no issue as the user shall always include the address offset
during the compilation phase. Otherwise, the code shall execute the
default address offset. Besides that, this also provides the
flexibility to user to customize their SoC design by not restricted
to the default address.

SDMMC block size. It was changed due to the need when boot to Linux.
Kernel.itb size is big thus we have to increase the available reading
block size. Otherwise for normal U-boot and Zephyr it shall not be
reading a big block size to avoid "garbage" data.

Change-Id: I1c2a22db28bf0ada734563e40efd4f5749951273
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset

This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Th

fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset

This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.

Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): direct boot from TF-A to Linux for Agilex

Enable and update code for TF-A direct boot Linux
for Agilex platform.

Change-Id: Id95986b7015a2a01f0aff80e1c7d8f8bb8fb4637
Signed-off-by: Sie

feat(intel): direct boot from TF-A to Linux for Agilex

Enable and update code for TF-A direct boot Linux
for Agilex platform.

Change-Id: Id95986b7015a2a01f0aff80e1c7d8f8bb8fb4637
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge "fix(intel): implement soc and lwsoc bridge control for burst speed" into integration

fix(intel): implement soc and lwsoc bridge control for burst speed

Implement burst speed read/write for SOC and LWSOC. Set bridge control
register to enable the register bit

Change-Id: I815b912cb90

fix(intel): implement soc and lwsoc bridge control for burst speed

Implement burst speed read/write for SOC and LWSOC. Set bridge control
register to enable the register bit

Change-Id: I815b912cb90d79a548163d198eea177d70dfbc0d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): update hand-off data to include agilex5 params

Update hand-off data structure to include agilex5
platform specific parameters.

Change-Id: Ic610e2d8da7488e49462293d13293e26520579e2
Sign

feat(intel): update hand-off data to include agilex5 params

Update hand-off data structure to include agilex5
platform specific parameters.

Change-Id: Ic610e2d8da7488e49462293d13293e26520579e2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): update mailbox SDM printout message" into integration

Merge "fix(intel): fix bridge enable and disable function" into integration

Merge "fix(intel): update outdated code for Linux direct boot" into integration

fix(intel): fix bridge enable and disable function

1. hps reset and reboot spec is missing ack clear status step
2. software workaround for bridge timeout
3. f2sdram bridge quick write thru failed
4

fix(intel): fix bridge enable and disable function

1. hps reset and reboot spec is missing ack clear status step
2. software workaround for bridge timeout
3. f2sdram bridge quick write thru failed
4. bridge timeout workaround for F2SOC and F2SDRAM


Change-Id: Ide4210ff862531f82e083633af385b559ffbe16b
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update outdated code for Linux direct boot

1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status

Change-Id: I33905508aceb258ac8759c10079b2af977df

fix(intel): update outdated code for Linux direct boot

1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status

Change-Id: I33905508aceb258ac8759c10079b2af977df0e0a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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