1# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 2# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 3# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 4# 5# SPDX-License-Identifier: BSD-3-Clause 6 7PLAT_PATH := plat/amd/versal2 8 9# A78 Erratum for SoC 10ERRATA_A78_AE_1941500 := 1 11ERRATA_A78_AE_1951502 := 1 12ERRATA_A78_AE_2376748 := 1 13ERRATA_A78_AE_2395408 := 1 14ERRATA_ABI_SUPPORT := 1 15 16# Platform Supports Armv8.2 extensions 17ARM_ARCH_MAJOR := 8 18ARM_ARCH_MINOR := 2 19 20override PROGRAMMABLE_RESET_ADDRESS := 1 21PSCI_EXTENDED_STATE_ID := 1 22SEPARATE_CODE_AND_RODATA := 1 23override RESET_TO_BL31 := 1 24PL011_GENERIC_UART := 1 25IPI_CRC_CHECK := 0 26GIC_ENABLE_V4_EXTN := 0 27GICV3_SUPPORT_GIC600 := 1 28 29override CTX_INCLUDE_AARCH32_REGS := 0 30 31# Platform to support Dynamic XLAT Table by default 32override PLAT_XLAT_TABLES_DYNAMIC := 1 33$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC)) 34 35ifdef MEM_BASE 36 $(eval $(call add_define,MEM_BASE)) 37 38 ifndef MEM_SIZE 39 $(error "MEM_BASE defined without MEM_SIZE") 40 endif 41 $(eval $(call add_define,MEM_SIZE)) 42 43 ifdef MEM_PROGBITS_SIZE 44 $(eval $(call add_define,MEM_PROGBITS_SIZE)) 45 endif 46endif 47 48ifdef BL32_MEM_BASE 49 $(eval $(call add_define,BL32_MEM_BASE)) 50 51 ifndef BL32_MEM_SIZE 52 $(error "BL32_MEM_BASE defined without BL32_MEM_SIZE") 53 endif 54 $(eval $(call add_define,BL32_MEM_SIZE)) 55endif 56 57ifdef IPI_CRC_CHECK 58 $(eval $(call add_define,IPI_CRC_CHECK)) 59endif 60 61USE_COHERENT_MEM := 0 62HW_ASSISTED_COHERENCY := 1 63 64VERSAL2_CONSOLE ?= pl011 65ifeq (${VERSAL2_CONSOLE}, $(filter ${VERSAL2_CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none)) 66 else 67 $(error "Please define VERSAL2_CONSOLE") 68 endif 69 70$(eval $(call add_define_val,VERSAL2_CONSOLE,VERSAL2_CONSOLE_ID_${VERSAL2_CONSOLE})) 71 72# Runtime console in default console in DEBUG build 73ifeq ($(DEBUG), 1) 74CONSOLE_RUNTIME ?= pl011 75endif 76 77# Runtime console 78ifdef CONSOLE_RUNTIME 79ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb)) 80$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME})) 81else 82 $(error "Please define CONSOLE_RUNTIME") 83endif 84endif 85 86 87ifdef XILINX_OF_BOARD_DTB_ADDR 88$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR)) 89endif 90 91PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 92 -Iplat/xilinx/common/include/ \ 93 -Iplat/xilinx/common/ipi_mailbox_service/ \ 94 -I${PLAT_PATH}/include/ \ 95 -Iplat/xilinx/versal/pm_service/ 96 97# Include GICv3 driver files 98include drivers/arm/gic/v3/gicv3.mk 99include lib/xlat_tables_v2/xlat_tables.mk 100include lib/libfdt/libfdt.mk 101 102PLAT_BL_COMMON_SOURCES := \ 103 drivers/arm/dcc/dcc_console.c \ 104 drivers/delay_timer/delay_timer.c \ 105 drivers/delay_timer/generic_delay_timer.c \ 106 ${GICV3_SOURCES} \ 107 drivers/arm/pl011/aarch64/pl011_console.S \ 108 plat/common/aarch64/crash_console_helpers.S \ 109 plat/arm/common/arm_common.c \ 110 plat/common/plat_gicv3.c \ 111 ${PLAT_PATH}/aarch64/helpers.S \ 112 ${PLAT_PATH}/aarch64/common.c \ 113 ${PLAT_PATH}/plat_topology.c \ 114 ${XLAT_TABLES_LIB_SRCS} 115 116BL31_SOURCES += drivers/arm/cci/cci.c \ 117 lib/cpus/aarch64/cortex_a78_ae.S \ 118 lib/cpus/aarch64/cortex_a78.S \ 119 plat/common/plat_psci_common.c \ 120 drivers/scmi-msg/base.c \ 121 drivers/scmi-msg/entry.c \ 122 drivers/scmi-msg/smt.c \ 123 drivers/scmi-msg/clock.c \ 124 drivers/scmi-msg/power_domain.c \ 125 drivers/scmi-msg/reset_domain.c \ 126 ${PLAT_PATH}/scmi.c 127 128BL31_SOURCES += ${PLAT_PATH}/plat_psci.c 129 130BL31_SOURCES += plat/xilinx/common/plat_fdt.c \ 131 common/fdt_wrappers.c \ 132 plat/xilinx/common/plat_fdt.c \ 133 plat/xilinx/common/plat_console.c \ 134 plat/xilinx/common/plat_startup.c \ 135 plat/xilinx/common/ipi.c \ 136 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ 137 ${PLAT_PATH}/soc_ipi.c \ 138 plat/xilinx/common/versal.c \ 139 ${PLAT_PATH}/bl31_setup.c \ 140 common/fdt_fixup.c \ 141 common/fdt_wrappers.c \ 142 ${LIBFDT_SRCS} \ 143 ${PLAT_PATH}/sip_svc_setup.c \ 144 ${PLAT_PATH}/gicv3.c 145 146ifeq (${ERRATA_ABI_SUPPORT}, 1) 147# enable the cpu macros for errata abi interface 148CORTEX_A78_AE_H_INC := 1 149$(eval $(call add_define, CORTEX_A78_AE_H_INC)) 150endif 151