1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <common/interrupt_props.h> 14 #include <common/tbbr/tbbr_img_def.h> 15 #include <plat/common/common_def.h> 16 #include "socfpga_plat_def.h" 17 18 /* Platform Type */ 19 #define PLAT_SOCFPGA_STRATIX10 1 20 #define PLAT_SOCFPGA_AGILEX 2 21 #define PLAT_SOCFPGA_N5X 3 22 #define PLAT_SOCFPGA_AGILEX5 4 23 #define SIMICS_RUN 1 24 #define MAX_IO_MTD_DEVICES U(1) 25 26 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ 27 #define PLAT_CPU_RELEASE_ADDR 0xffd12210 28 29 /* Magic word to indicate L2 reset is completed */ 30 #define L2_RESET_DONE_STATUS 0x1228E5E7 31 32 /* Magic word to differentiate for SMP secondary core boot request */ 33 #define SMP_SEC_CORE_BOOT_REQ 0x1228E5E8 34 35 /* Define next boot image name and offset */ 36 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ 37 #ifdef PRELOADED_BL33_BASE 38 #define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 39 #else 40 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 41 #define PLAT_NS_IMAGE_OFFSET 0x80200000 42 #else 43 #define PLAT_NS_IMAGE_OFFSET 0x10000000 44 #endif 45 #endif /* #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 */ 46 47 #define PLAT_QSPI_DATA_BASE (0x3C00000) 48 #define PLAT_NAND_DATA_BASE (0x0200000) 49 #define PLAT_SDMMC_DATA_BASE (0x0) 50 51 52 /******************************************************************************* 53 * Platform binary types for linking 54 ******************************************************************************/ 55 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 56 #define PLATFORM_LINKER_ARCH aarch64 57 58 /* SoCFPGA supports up to 124GB RAM */ 59 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 60 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 61 62 63 /******************************************************************************* 64 * Generic platform constants 65 ******************************************************************************/ 66 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 67 68 /* Size of cacheable stacks */ 69 #define PLATFORM_STACK_SIZE 0x2000 70 71 /* PSCI related constant */ 72 #define PLAT_NUM_POWER_DOMAINS 5 73 #define PLAT_MAX_PWR_LVL 1 74 #define PLAT_MAX_RET_STATE 1 75 #define PLAT_MAX_OFF_STATE 2 76 #define PLATFORM_SYSTEM_COUNT U(1) 77 #define PLATFORM_CLUSTER_COUNT U(1) 78 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 79 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 80 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 81 PLATFORM_CLUSTER0_CORE_COUNT) 82 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 83 84 /* Interrupt related constant */ 85 86 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 87 88 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 89 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 90 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 91 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 92 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 93 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 94 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 95 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 96 97 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 98 #define TSP_SEC_MEM_BASE BL32_BASE 99 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 100 101 102 /******************************************************************************* 103 * BL31 specific defines. 104 ******************************************************************************/ 105 /* 106 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 107 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 108 * little space for growth. 109 */ 110 111 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 112 113 #define BL1_RO_BASE (0xffe00000) 114 #define BL1_RO_LIMIT (0xffe0f000) 115 #define BL1_RW_BASE (0xffe10000) 116 #define BL1_RW_LIMIT (0xffe1ffff) 117 #define BL1_RW_SIZE (0x14000) 118 119 #define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET 120 121 #define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) 122 #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) 123 124 #define CMP_ENTRY 0xFFE3EFF8 125 126 #define PLAT_SEC_WARM_ENTRY 0 127 128 /******************************************************************************* 129 * Platform specific page table and MMU setup constants 130 ******************************************************************************/ 131 #define MAX_XLAT_TABLES 8 132 #define MAX_MMAP_REGIONS 16 133 134 /******************************************************************************* 135 * Declarations and constants to access the mailboxes safely. Each mailbox is 136 * aligned on the biggest cache line size in the platform. This is known only 137 * to the platform as it might have a combination of integrated and external 138 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 139 * line at any cache level. They could belong to different cpus/clusters & 140 * get written while being protected by different locks causing corruption of 141 * a valid mailbox address. 142 ******************************************************************************/ 143 #define CACHE_WRITEBACK_SHIFT 6 144 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 145 146 /******************************************************************************* 147 * UART related constants 148 ******************************************************************************/ 149 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 150 #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE 151 152 #define PLAT_BAUDRATE (115200) 153 #define PLAT_UART_CLOCK (100000000) 154 155 /******************************************************************************* 156 * PHY related constants 157 ******************************************************************************/ 158 159 #define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII 160 #define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII 161 #define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII 162 163 /******************************************************************************* 164 * GIC related constants 165 ******************************************************************************/ 166 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 167 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 168 169 /******************************************************************************* 170 * System counter frequency related constants 171 ******************************************************************************/ 172 173 /* 174 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 175 * terminology. On a GICv2 system or mode, the lists will be merged and treated 176 * as Group 0 interrupts. 177 */ 178 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 179 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 180 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 181 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 182 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 183 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 184 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 185 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 186 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 187 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 188 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 189 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 190 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 191 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 192 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 193 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 194 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 195 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 196 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 197 198 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 199 200 #define MAX_IO_HANDLES 4 201 #define MAX_IO_DEVICES 4 202 #define MAX_IO_BLOCK_DEVICES 2 203 204 #ifndef __ASSEMBLER__ 205 struct socfpga_bl31_params { 206 param_header_t h; 207 image_info_t *bl31_image_info; 208 entry_point_info_t *bl32_ep_info; 209 image_info_t *bl32_image_info; 210 entry_point_info_t *bl33_ep_info; 211 image_info_t *bl33_image_info; 212 }; 213 #endif 214 215 #endif /* PLATFORM_DEF_H */ 216