1/* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <cpu_macros.S> 12#include <platform_def.h> 13#include <el3_common_macros.S> 14 15 .globl plat_secondary_cold_boot_setup 16 .globl platform_is_primary_cpu 17 .globl plat_is_my_cpu_primary 18 .globl plat_my_core_pos 19 .globl plat_crash_console_init 20 .globl plat_crash_console_putc 21 .globl plat_crash_console_flush 22 .globl platform_mem_init 23 .globl plat_secondary_cpus_bl31_entry 24 .globl invalidate_cache_low_el 25 26 .globl plat_get_my_entrypoint 27 28 /* ----------------------------------------------------- 29 * void plat_secondary_cold_boot_setup (void); 30 * 31 * This function performs any platform specific actions 32 * needed for a secondary cpu after a cold reset e.g 33 * mark the cpu's presence, mechanism to place it in a 34 * holding pen etc. 35 * ----------------------------------------------------- 36 */ 37func plat_secondary_cold_boot_setup 38 /* Wait until the it gets reset signal from rstmgr gets populated */ 39poll_mailbox: 40#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 41 mov_imm x0, PLAT_SEC_ENTRY 42 cbz x0, poll_mailbox 43 br x0 44#else 45 wfi 46 mov_imm x0, PLAT_SEC_ENTRY 47 ldr x1, [x0] 48 mov_imm x2, PLAT_CPUID_RELEASE 49 ldr x3, [x2] 50 mrs x4, mpidr_el1 51 and x4, x4, #0xff 52 cmp x3, x4 53 b.ne poll_mailbox 54 br x1 55#endif 56endfunc plat_secondary_cold_boot_setup 57 58#if ((PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10) || \ 59 (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX) || \ 60 (PLATFORM_MODEL == PLAT_SOCFPGA_N5X)) 61 62func platform_is_primary_cpu 63 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 64 cmp x0, #PLAT_PRIMARY_CPU 65 cset x0, eq 66 ret 67endfunc platform_is_primary_cpu 68 69#else 70 71func platform_is_primary_cpu 72 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 73 cmp x0, #(PLAT_PRIMARY_CPU_A76) 74 b.eq primary_cpu 75 cmp x0, #(PLAT_PRIMARY_CPU_A55) 76 b.eq primary_cpu 77primary_cpu: 78 cset x0, eq 79 ret 80endfunc platform_is_primary_cpu 81 82#endif 83 84func plat_is_my_cpu_primary 85 mrs x0, mpidr_el1 86 b platform_is_primary_cpu 87endfunc plat_is_my_cpu_primary 88 89func plat_my_core_pos 90 mrs x0, mpidr_el1 91 and x1, x0, #MPIDR_CPU_MASK 92 and x0, x0, #MPIDR_CLUSTER_MASK 93#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 94 add x0, x1, x0, LSR #8 95#else 96 add x0, x1, x0, LSR #6 97#endif 98 ret 99endfunc plat_my_core_pos 100 101func warm_reset_req 102#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 103 bl plat_is_my_cpu_primary 104 cbnz x0, warm_reset 105warm_reset: 106 mov_imm x1, PLAT_SEC_ENTRY 107 str xzr, [x1] 108 mrs x1, rmr_el3 109 orr x1, x1, #0x02 110 msr rmr_el3, x1 111 isb 112 dsb sy 113#else 114 str xzr, [x4] 115 bl plat_is_my_cpu_primary 116 cbz x0, cpu_in_wfi 117 mov_imm x1, PLAT_SEC_ENTRY 118 str xzr, [x1] 119 mrs x1, rmr_el3 120 orr x1, x1, #0x02 121 msr rmr_el3, x1 122 isb 123 dsb sy 124cpu_in_wfi: 125 wfi 126 b cpu_in_wfi 127#endif 128endfunc warm_reset_req 129 130/* TODO: Zephyr warm reset test */ 131#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 132func plat_get_my_entrypoint 133 ldr x4, =L2_RESET_DONE_REG 134 ldr x5, [x4] 135 ldr x1, =PLAT_L2_RESET_REQ 136 cmp x1, x5 137 b.eq zephyr_reset_req 138 mov_imm x1, PLAT_SEC_ENTRY 139 ldr x0, [x1] 140 ret 141zephyr_reset_req: 142 ldr x0, =0x00 143 ret 144endfunc plat_get_my_entrypoint 145#else 146func plat_get_my_entrypoint 147 ldr x4, =L2_RESET_DONE_REG 148 ldr x5, [x4] 149 ldr x1, =L2_RESET_DONE_STATUS 150 cmp x1, x5 151 b.eq warm_reset_req 152 mov_imm x1, PLAT_SEC_ENTRY 153 ldr x0, [x1] 154 ret 155endfunc plat_get_my_entrypoint 156#endif 157 158 /* --------------------------------------------- 159 * int plat_crash_console_init(void) 160 * Function to initialize the crash console 161 * without a C Runtime to print crash report. 162 * Clobber list : x0, x1, x2 163 * --------------------------------------------- 164 */ 165func plat_crash_console_init 166 mov_imm x0, CRASH_CONSOLE_BASE 167 mov_imm x1, PLAT_UART_CLOCK 168 mov_imm x2, PLAT_BAUDRATE 169 b console_16550_core_init 170endfunc plat_crash_console_init 171 172 /* --------------------------------------------- 173 * int plat_crash_console_putc(void) 174 * Function to print a character on the crash 175 * console without a C Runtime. 176 * Clobber list : x1, x2 177 * --------------------------------------------- 178 */ 179func plat_crash_console_putc 180 mov_imm x1, CRASH_CONSOLE_BASE 181 b console_16550_core_putc 182endfunc plat_crash_console_putc 183 184func plat_crash_console_flush 185 mov_imm x0, CRASH_CONSOLE_BASE 186 b console_16550_core_flush 187endfunc plat_crash_console_flush 188 189 190 /* -------------------------------------------------------- 191 * void platform_mem_init (void); 192 * 193 * Any memory init, relocation to be done before the 194 * platform boots. Called very early in the boot process. 195 * -------------------------------------------------------- 196 */ 197func platform_mem_init 198 mov x0, #0 199 ret 200endfunc platform_mem_init 201 202 /* -------------------------------------------------------- 203 * macro plat_secondary_cpus_bl31_entry; 204 * 205 * el3_entrypoint_common init param configuration. 206 * Called very early in the secondary cores boot process. 207 * -------------------------------------------------------- 208 */ 209func plat_secondary_cpus_bl31_entry 210 el3_entrypoint_common \ 211 _init_sctlr=0 \ 212 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 213 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 214 _init_memory=1 \ 215 _init_c_runtime=1 \ 216 _exception_vectors=runtime_exceptions \ 217 _pie_fixup_size=BL31_LIMIT - BL31_BASE 218endfunc plat_secondary_cpus_bl31_entry 219 220/* -------------------------------------------------------- 221 * Invalidate for NS EL2 and EL1 222 * -------------------------------------------------------- 223 */ 224func invalidate_cache_low_el 225 mrs x0,SCR_EL3 226 orr x1,x0,#SCR_NS_BIT 227 msr SCR_EL3, x1 228 isb 229 tlbi ALLE2 230 dsb sy 231 tlbi ALLE1 232 dsb sy 233endfunc invalidate_cache_low_el 234