1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLAT_SOCFPGA_DEF_H 10 #define PLAT_SOCFPGA_DEF_H 11 12 #include "agilex5_memory_controller.h" 13 #include "agilex5_system_manager.h" 14 15 #include <platform_def.h> 16 17 /* Platform Setting */ 18 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 19 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 20 /* 1 = Flush cache, 0 = No cache flush. 21 * Default for Agilex5 is Cache flush. 22 */ 23 #define CACHE_FLUSH 1 24 #define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */ 25 #define XLAT_TABLES_V2 U(1) 26 #define PLAT_PRIMARY_CPU_A55 0x000 27 #define PLAT_PRIMARY_CPU_A76 0x200 28 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT 29 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 30 #define PLAT_L2_RESET_REQ 0xB007C0DE 31 #define PLAT_TIMER_BASE_ADDR 0x10D01000 32 33 /* System Counter */ 34 /* TODO: Update back to 400MHz. 35 * This shall be updated to read from L4 clock instead of hardcoded. 36 */ 37 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS U(400000000) 38 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 39 40 /* FPGA config helpers */ 41 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x80400000 42 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x82000000 43 44 /* QSPI Setting */ 45 #define CAD_QSPIDATA_OFST 0x10900000 46 #define CAD_QSPI_OFFSET 0x108d2000 47 48 /* Register Mapping */ 49 #define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000 50 #define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000 51 52 #define SOCFPGA_MMC_REG_BASE 0x10808000 53 #define SOCFPGA_MEMCTRL_REG_BASE 0x108CC000 54 #define SOCFPGA_RSTMGR_REG_BASE 0x10d11000 55 #define SOCFPGA_SYSMGR_REG_BASE 0x10d12000 56 #define SOCFPGA_PINMUX_REG_BASE 0x10d13000 57 #define SOCFPGA_NAND_REG_BASE 0x10B80000 58 #define SOCFPGA_ECC_QSPI_REG_BASE 0x10A22000 59 60 #define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000 61 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100 62 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200 63 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300 64 65 /* Define maximum page size for NAND flash devices */ 66 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x2000) 67 68 /******************************************************************************* 69 * Platform memory map related constants 70 ******************************************************************************/ 71 #define DRAM_BASE (0x80000000) 72 #define DRAM_SIZE (0x80000000) 73 74 #define OCRAM_BASE (0x00000000) 75 #define OCRAM_SIZE (0x00080000) 76 77 #define MEM64_BASE (0x0080000000) 78 #define MEM64_SIZE (0x0080000000) 79 80 //128MB PSS 81 #define PSS_BASE (0x10000000) 82 #define PSS_SIZE (0x08000000) 83 84 //64MB MPFE 85 #define MPFE_BASE (0x18000000) 86 #define MPFE_SIZE (0x04000000) 87 88 //16MB CCU 89 #define CCU_BASE (0x1C000000) 90 #define CCU_SIZE (0x01000000) 91 92 //1MB GIC 93 #define GIC_BASE (0x1D000000) 94 #define GIC_SIZE (0x00100000) 95 96 #define BL2_BASE (0x00000000) 97 #define BL2_LIMIT (0x0007E000) 98 99 #define BL31_BASE (0x80000000) 100 #define BL31_LIMIT (0x82000000) 101 /******************************************************************************* 102 * UART related constants 103 ******************************************************************************/ 104 #define PLAT_UART0_BASE (0x10C02000) 105 #define PLAT_UART1_BASE (0x10C02100) 106 107 /******************************************************************************* 108 * WDT related constants 109 ******************************************************************************/ 110 #define WDT_BASE (0x10D00200) 111 112 /******************************************************************************* 113 * GIC related constants 114 ******************************************************************************/ 115 #define PLAT_GIC_BASE (0x1D000000) 116 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x20000) 117 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x00000) 118 #define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x60000) 119 120 #define PLAT_INTEL_SOCFPGA_GICR_BASE PLAT_GICR_BASE 121 122 /******************************************************************************* 123 * SDMMC related pointer function 124 ******************************************************************************/ 125 #define SDMMC_READ_BLOCKS sdmmc_read_blocks 126 #define SDMMC_WRITE_BLOCKS sdmmc_write_blocks 127 128 /******************************************************************************* 129 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 130 * is done and HPS should trigger warm reset via RMR_EL3. 131 ******************************************************************************/ 132 #define L2_RESET_DONE_REG 0x10D12218 133 134 #endif /* PLAT_SOCFPGA_DEF_H */ 135