1 /* 2 * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/cadence/cdns_sdmmc.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/synopsys/dw_mmc.h> 18 #include <drivers/ti/uart/uart_16550.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 22 #include "agilex5_clock_manager.h" 23 #include "agilex5_ddr.h" 24 #include "agilex5_memory_controller.h" 25 #include "agilex5_mmc.h" 26 #include "agilex5_pinmux.h" 27 #include "agilex5_power_manager.h" 28 #include "agilex5_system_manager.h" 29 #include "ccu/ncore_ccu.h" 30 #include "combophy/combophy.h" 31 #include "nand/nand.h" 32 #include "qspi/cadence_qspi.h" 33 #include "sdmmc/sdmmc.h" 34 #include "socfpga_emac.h" 35 #include "socfpga_f2sdram_manager.h" 36 #include "socfpga_handoff.h" 37 #include "socfpga_mailbox.h" 38 #include "socfpga_private.h" 39 #include "socfpga_reset_manager.h" 40 #include "socfpga_ros.h" 41 #include "socfpga_vab.h" 42 #include "wdt/watchdog.h" 43 44 45 /* Declare mmc_info */ 46 static struct mmc_device_info mmc_info; 47 48 /* Declare cadence idmac descriptor */ 49 extern struct cdns_idmac_desc cdns_desc[8] __aligned(32); 50 51 const mmap_region_t agilex_plat_mmap[] = { 52 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 53 MT_MEMORY | MT_RW | MT_NS), 54 MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, 55 MT_DEVICE | MT_RW | MT_NS), 56 MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, 57 MT_DEVICE | MT_RW | MT_SECURE), 58 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 59 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 60 MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, 61 MT_DEVICE | MT_RW | MT_SECURE), 62 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 63 MT_DEVICE | MT_RW | MT_NS), 64 MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, 65 MT_DEVICE | MT_RW | MT_SECURE), 66 {0}, 67 }; 68 69 boot_source_type boot_source = BOOT_SOURCE; 70 71 void bl2_el3_early_platform_setup(u_register_t x0 __unused, 72 u_register_t x1 __unused, 73 u_register_t x2 __unused, 74 u_register_t x3 __unused) 75 { 76 static console_t console; 77 handoff reverse_handoff_ptr; 78 79 /* Enable nonsecure access for peripherals and other misc components */ 80 enable_nonsecure_access(); 81 82 /* Bring all the required peripherals out of reset */ 83 deassert_peripheral_reset(); 84 85 /* 86 * Initialize the UART console early in BL2 EL3 boot flow to get 87 * the error/notice messages wherever required. 88 */ 89 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 90 PLAT_BAUDRATE, &console); 91 92 /* Generic delay timer init */ 93 generic_delay_timer_init(); 94 95 socfpga_delay_timer_init(); 96 97 /* Get the handoff data */ 98 if ((socfpga_get_handoff(&reverse_handoff_ptr)) != 0) { 99 ERROR("SOCFPGA: Failed to get the correct handoff data\n"); 100 panic(); 101 } 102 103 /* Configure the pinmux */ 104 config_pinmux(&reverse_handoff_ptr); 105 106 /* Configure OCRAM to NON SECURE ACCESS */ 107 mmio_write_32(OCRAM_REGION_0_REG_BASE, OCRAM_NON_SECURE_ENABLE); 108 mmio_write_32(SOCFPGA_L4_PER_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT, 109 SOCFPGA_SDMMC_SECU_BIT_ENABLE); 110 mmio_write_32(SOCFPGA_L4_SYS_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT, 111 SOCFPGA_SDMMC_SECU_BIT_ENABLE); 112 mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE, 113 SOCFPGA_LWSOC2FPGA_ENABLE); 114 115 /* Configure the clock manager */ 116 if ((config_clkmgr_handoff(&reverse_handoff_ptr)) != 0) { 117 ERROR("SOCFPGA: Failed to initialize the clock manager\n"); 118 panic(); 119 } 120 121 /* Configure power manager PSS SRAM power gate */ 122 config_pwrmgr_handoff(&reverse_handoff_ptr); 123 124 /* Initialize the mailbox to enable communication between HPS and SDM */ 125 mailbox_init(); 126 127 /* Perform a handshake with certain peripherals before issuing a reset */ 128 config_hps_hs_before_warm_reset(); 129 130 /* TODO: watchdog init */ 131 //watchdog_init(clkmgr_get_rate(CLKMGR_WDT_CLK_ID)); 132 133 /* Initialize the CCU module for hardware cache coherency */ 134 init_ncore_ccu(); 135 136 socfpga_emac_init(); 137 138 /* DDR and IOSSM driver init */ 139 agilex5_ddr_init(&reverse_handoff_ptr); 140 141 if (combo_phy_init(&reverse_handoff_ptr) != 0) { 142 ERROR("SOCFPGA: Combo Phy initialization failed\n"); 143 } 144 145 /* Enable FPGA bridges as required */ 146 if (!intel_mailbox_is_fpga_not_ready()) { 147 socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK | 148 FPGA2SOC_MASK | F2SDRAM0_MASK); 149 } 150 } 151 152 void bl2_el3_plat_arch_setup(void) 153 { 154 handoff reverse_handoff_ptr; 155 unsigned long offset = 0; 156 157 struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc, get_mmc_clk()); 158 159 mmc_info.mmc_dev_type = MMC_DEVICE_TYPE; 160 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 161 162 /* Request ownership and direct access to QSPI */ 163 mailbox_hps_qspi_enable(); 164 165 switch (boot_source) { 166 case BOOT_SOURCE_SDMMC: 167 NOTICE("SDMMC boot\n"); 168 cdns_mmc_init(¶ms, &mmc_info); 169 socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE); 170 break; 171 172 case BOOT_SOURCE_QSPI: 173 NOTICE("QSPI boot\n"); 174 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 175 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 176 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 177 if (ros_qspi_get_ssbl_offset(&offset) != ROS_RET_OK) { 178 offset = PLAT_QSPI_DATA_BASE; 179 } 180 socfpga_io_setup(boot_source, offset); 181 break; 182 183 case BOOT_SOURCE_NAND: 184 NOTICE("NAND boot\n"); 185 nand_init(&reverse_handoff_ptr); 186 socfpga_io_setup(boot_source, PLAT_NAND_DATA_BASE); 187 break; 188 189 default: 190 ERROR("Unsupported boot source\n"); 191 panic(); 192 break; 193 } 194 } 195 196 uint32_t get_spsr_for_bl33_entry(void) 197 { 198 unsigned long el_status; 199 unsigned int mode; 200 uint32_t spsr; 201 202 /* Figure out what mode we enter the non-secure world in */ 203 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 204 el_status &= ID_AA64PFR0_ELX_MASK; 205 206 mode = (el_status) ? MODE_EL2 : MODE_EL1; 207 208 /* 209 * TODO: Consider the possibility of specifying the SPSR in 210 * the FIP ToC and allowing the platform to have a say as 211 * well. 212 */ 213 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 214 return spsr; 215 } 216 217 int bl2_plat_handle_post_image_load(unsigned int image_id) 218 { 219 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 220 221 assert(bl_mem_params); 222 223 #if SOCFPGA_SECURE_VAB_AUTH 224 /* 225 * VAB Authentication start here. 226 * If failed to authenticate, shall not proceed to process BL31 and hang. 227 */ 228 int ret = 0; 229 230 ret = socfpga_vab_init(image_id); 231 if (ret < 0) { 232 ERROR("SOCFPGA VAB Authentication failed\n"); 233 wfi(); 234 } 235 #endif 236 237 switch (image_id) { 238 case BL33_IMAGE_ID: 239 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 240 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 241 break; 242 default: 243 break; 244 } 245 246 return 0; 247 } 248 249 /******************************************************************************* 250 * Perform any BL3-1 platform setup code 251 ******************************************************************************/ 252 void bl2_platform_setup(void) 253 { 254 } 255