1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/mpam.h> 32 #include <lib/extensions/pmuv3.h> 33 #include <lib/extensions/sme.h> 34 #include <lib/extensions/spe.h> 35 #include <lib/extensions/sve.h> 36 #include <lib/extensions/sys_reg_trace.h> 37 #include <lib/extensions/tcr2.h> 38 #include <lib/extensions/trbe.h> 39 #include <lib/extensions/trf.h> 40 #include <lib/utils.h> 41 42 #if ENABLE_FEAT_TWED 43 /* Make sure delay value fits within the range(0-15) */ 44 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 45 #endif /* ENABLE_FEAT_TWED */ 46 47 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 48 static bool has_secure_perworld_init; 49 50 static void manage_extensions_common(cpu_context_t *ctx); 51 static void manage_extensions_nonsecure(cpu_context_t *ctx); 52 static void manage_extensions_secure(cpu_context_t *ctx); 53 static void manage_extensions_secure_per_world(void); 54 55 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 56 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 57 { 58 u_register_t sctlr_elx, actlr_elx; 59 60 /* 61 * Initialise SCTLR_EL1 to the reset value corresponding to the target 62 * execution state setting all fields rather than relying on the hw. 63 * Some fields have architecturally UNKNOWN reset values and these are 64 * set to zero. 65 * 66 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 67 * 68 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 69 * required by PSCI specification) 70 */ 71 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 72 if (GET_RW(ep->spsr) == MODE_RW_64) { 73 sctlr_elx |= SCTLR_EL1_RES1; 74 } else { 75 /* 76 * If the target execution state is AArch32 then the following 77 * fields need to be set. 78 * 79 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 80 * instructions are not trapped to EL1. 81 * 82 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 83 * instructions are not trapped to EL1. 84 * 85 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 86 * CP15DMB, CP15DSB, and CP15ISB instructions. 87 */ 88 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 89 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 90 } 91 92 /* 93 * If workaround of errata 764081 for Cortex-A75 is used then set 94 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 95 */ 96 if (errata_a75_764081_applies()) { 97 sctlr_elx |= SCTLR_IESB_BIT; 98 } 99 100 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 101 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 102 103 /* 104 * Base the context ACTLR_EL1 on the current value, as it is 105 * implementation defined. The context restore process will write 106 * the value from the context to the actual register and can cause 107 * problems for processor cores that don't expect certain bits to 108 * be zero. 109 */ 110 actlr_elx = read_actlr_el1(); 111 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 112 } 113 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 114 115 /****************************************************************************** 116 * This function performs initializations that are specific to SECURE state 117 * and updates the cpu context specified by 'ctx'. 118 *****************************************************************************/ 119 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 120 { 121 u_register_t scr_el3; 122 el3_state_t *state; 123 124 state = get_el3state_ctx(ctx); 125 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 126 127 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 128 /* 129 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 130 * indicated by the interrupt routing model for BL31. 131 */ 132 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 133 #endif 134 135 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 136 if (is_feat_mte2_supported()) { 137 scr_el3 |= SCR_ATA_BIT; 138 } 139 140 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 141 142 /* 143 * Initialize EL1 context registers unless SPMC is running 144 * at S-EL2. 145 */ 146 #if (!SPMD_SPM_AT_SEL2) 147 setup_el1_context(ctx, ep); 148 #endif 149 150 manage_extensions_secure(ctx); 151 152 /** 153 * manage_extensions_secure_per_world api has to be executed once, 154 * as the registers getting initialised, maintain constant value across 155 * all the cpus for the secure world. 156 * Henceforth, this check ensures that the registers are initialised once 157 * and avoids re-initialization from multiple cores. 158 */ 159 if (!has_secure_perworld_init) { 160 manage_extensions_secure_per_world(); 161 } 162 } 163 164 #if ENABLE_RME 165 /****************************************************************************** 166 * This function performs initializations that are specific to REALM state 167 * and updates the cpu context specified by 'ctx'. 168 *****************************************************************************/ 169 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 170 { 171 u_register_t scr_el3; 172 el3_state_t *state; 173 174 state = get_el3state_ctx(ctx); 175 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 176 177 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 178 179 /* CSV2 version 2 and above */ 180 if (is_feat_csv2_2_supported()) { 181 /* Enable access to the SCXTNUM_ELx registers. */ 182 scr_el3 |= SCR_EnSCXT_BIT; 183 } 184 185 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 186 } 187 #endif /* ENABLE_RME */ 188 189 /****************************************************************************** 190 * This function performs initializations that are specific to NON-SECURE state 191 * and updates the cpu context specified by 'ctx'. 192 *****************************************************************************/ 193 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 194 { 195 u_register_t scr_el3; 196 el3_state_t *state; 197 198 state = get_el3state_ctx(ctx); 199 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 200 201 /* SCR_NS: Set the NS bit */ 202 scr_el3 |= SCR_NS_BIT; 203 204 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 205 if (is_feat_mte2_supported()) { 206 scr_el3 |= SCR_ATA_BIT; 207 } 208 209 #if !CTX_INCLUDE_PAUTH_REGS 210 /* 211 * Pointer Authentication feature, if present, is always enabled by default 212 * for Non secure lower exception levels. We do not have an explicit 213 * flag to set it. 214 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 215 * exception levels of secure and realm worlds. 216 * 217 * To prevent the leakage between the worlds during world switch, 218 * we enable it only for the non-secure world. 219 * 220 * If the Secure/realm world wants to use pointer authentication, 221 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 222 * it will be enabled globally for all the contexts. 223 * 224 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 225 * other than EL3 226 * 227 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 228 * than EL3 229 */ 230 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 231 232 #endif /* CTX_INCLUDE_PAUTH_REGS */ 233 234 #if HANDLE_EA_EL3_FIRST_NS 235 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 236 scr_el3 |= SCR_EA_BIT; 237 #endif 238 239 #if RAS_TRAP_NS_ERR_REC_ACCESS 240 /* 241 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 242 * and RAS ERX registers from EL1 and EL2(from any security state) 243 * are trapped to EL3. 244 * Set here to trap only for NS EL1/EL2 245 * 246 */ 247 scr_el3 |= SCR_TERR_BIT; 248 #endif 249 250 /* CSV2 version 2 and above */ 251 if (is_feat_csv2_2_supported()) { 252 /* Enable access to the SCXTNUM_ELx registers. */ 253 scr_el3 |= SCR_EnSCXT_BIT; 254 } 255 256 #ifdef IMAGE_BL31 257 /* 258 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 259 * indicated by the interrupt routing model for BL31. 260 */ 261 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 262 #endif 263 264 if (is_feat_the_supported()) { 265 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 266 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 267 */ 268 scr_el3 |= SCR_RCWMASKEn_BIT; 269 } 270 271 if (is_feat_sctlr2_supported()) { 272 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 273 * SCTLR2_ELx registers. 274 */ 275 scr_el3 |= SCR_SCTLR2En_BIT; 276 } 277 278 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 279 280 /* Initialize EL2 context registers */ 281 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 282 283 /* 284 * Initialize SCTLR_EL2 context register with reset value. 285 */ 286 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 287 288 if (is_feat_hcx_supported()) { 289 /* 290 * Initialize register HCRX_EL2 with its init value. 291 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 292 * chance that this can lead to unexpected behavior in lower 293 * ELs that have not been updated since the introduction of 294 * this feature if not properly initialized, especially when 295 * it comes to those bits that enable/disable traps. 296 */ 297 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 298 HCRX_EL2_INIT_VAL); 299 } 300 301 if (is_feat_fgt_supported()) { 302 /* 303 * Initialize HFG*_EL2 registers with a default value so legacy 304 * systems unaware of FEAT_FGT do not get trapped due to their lack 305 * of initialization for this feature. 306 */ 307 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 308 HFGITR_EL2_INIT_VAL); 309 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 310 HFGRTR_EL2_INIT_VAL); 311 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 312 HFGWTR_EL2_INIT_VAL); 313 } 314 #else 315 /* Initialize EL1 context registers */ 316 setup_el1_context(ctx, ep); 317 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 318 319 manage_extensions_nonsecure(ctx); 320 } 321 322 /******************************************************************************* 323 * The following function performs initialization of the cpu_context 'ctx' 324 * for first use that is common to all security states, and sets the 325 * initial entrypoint state as specified by the entry_point_info structure. 326 * 327 * The EE and ST attributes are used to configure the endianness and secure 328 * timer availability for the new execution context. 329 ******************************************************************************/ 330 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 331 { 332 u_register_t scr_el3; 333 u_register_t mdcr_el3; 334 el3_state_t *state; 335 gp_regs_t *gp_regs; 336 337 state = get_el3state_ctx(ctx); 338 339 /* Clear any residual register values from the context */ 340 zeromem(ctx, sizeof(*ctx)); 341 342 /* 343 * The lower-EL context is zeroed so that no stale values leak to a world. 344 * It is assumed that an all-zero lower-EL context is good enough for it 345 * to boot correctly. However, there are very few registers where this 346 * is not true and some values need to be recreated. 347 */ 348 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 349 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 350 351 /* 352 * These bits are set in the gicv3 driver. Losing them (especially the 353 * SRE bit) is problematic for all worlds. Henceforth recreate them. 354 */ 355 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 356 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 357 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 358 359 /* 360 * The actlr_el2 register can be initialized in platform's reset handler 361 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 362 */ 363 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 364 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 365 366 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 367 scr_el3 = SCR_RESET_VAL; 368 369 /* 370 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 371 * EL2, EL1 and EL0 are not trapped to EL3. 372 * 373 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 374 * EL2, EL1 and EL0 are not trapped to EL3. 375 * 376 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 377 * both Security states and both Execution states. 378 * 379 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 380 * Non-secure memory. 381 */ 382 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 383 384 scr_el3 |= SCR_SIF_BIT; 385 386 /* 387 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 388 * Exception level as specified by SPSR. 389 */ 390 if (GET_RW(ep->spsr) == MODE_RW_64) { 391 scr_el3 |= SCR_RW_BIT; 392 } 393 394 /* 395 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 396 * Secure timer registers to EL3, from AArch64 state only, if specified 397 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 398 * bit always behaves as 1 (i.e. secure physical timer register access 399 * is not trapped) 400 */ 401 if (EP_GET_ST(ep->h.attr) != 0U) { 402 scr_el3 |= SCR_ST_BIT; 403 } 404 405 /* 406 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 407 * SCR_EL3.HXEn. 408 */ 409 if (is_feat_hcx_supported()) { 410 scr_el3 |= SCR_HXEn_BIT; 411 } 412 413 /* 414 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 415 * registers are trapped to EL3. 416 */ 417 #if ENABLE_FEAT_RNG_TRAP 418 scr_el3 |= SCR_TRNDR_BIT; 419 #endif 420 421 #if FAULT_INJECTION_SUPPORT 422 /* Enable fault injection from lower ELs */ 423 scr_el3 |= SCR_FIEN_BIT; 424 #endif 425 426 #if CTX_INCLUDE_PAUTH_REGS 427 /* 428 * Enable Pointer Authentication globally for all the worlds. 429 * 430 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 431 * other than EL3 432 * 433 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 434 * than EL3 435 */ 436 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 437 #endif /* CTX_INCLUDE_PAUTH_REGS */ 438 439 /* 440 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 441 */ 442 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 443 scr_el3 |= SCR_TCR2EN_BIT; 444 } 445 446 /* 447 * SCR_EL3.PIEN: Enable permission indirection and overlay 448 * registers for AArch64 if present. 449 */ 450 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 451 scr_el3 |= SCR_PIEN_BIT; 452 } 453 454 /* 455 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 456 */ 457 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 458 scr_el3 |= SCR_GCSEn_BIT; 459 } 460 461 /* 462 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 463 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 464 * next mode is Hyp. 465 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 466 * same conditions as HVC instructions and when the processor supports 467 * ARMv8.6-FGT. 468 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 469 * CNTPOFF_EL2 register under the same conditions as HVC instructions 470 * and when the processor supports ECV. 471 */ 472 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 473 || ((GET_RW(ep->spsr) != MODE_RW_64) 474 && (GET_M32(ep->spsr) == MODE32_hyp))) { 475 scr_el3 |= SCR_HCE_BIT; 476 477 if (is_feat_fgt_supported()) { 478 scr_el3 |= SCR_FGTEN_BIT; 479 } 480 481 if (is_feat_ecv_supported()) { 482 scr_el3 |= SCR_ECVEN_BIT; 483 } 484 } 485 486 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 487 if (is_feat_twed_supported()) { 488 /* Set delay in SCR_EL3 */ 489 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 490 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 491 << SCR_TWEDEL_SHIFT); 492 493 /* Enable WFE delay */ 494 scr_el3 |= SCR_TWEDEn_BIT; 495 } 496 497 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 498 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 499 if (is_feat_sel2_supported()) { 500 scr_el3 |= SCR_EEL2_BIT; 501 } 502 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 503 504 /* 505 * Populate EL3 state so that we've the right context 506 * before doing ERET 507 */ 508 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 509 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 510 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 511 512 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 513 mdcr_el3 = MDCR_EL3_RESET_VAL; 514 515 /* --------------------------------------------------------------------- 516 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 517 * Some fields are architecturally UNKNOWN on reset. 518 * 519 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 520 * Debug exceptions, other than Breakpoint Instruction exceptions, are 521 * disabled from all ELs in Secure state. 522 * 523 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 524 * privileged debug from S-EL1. 525 * 526 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 527 * access to the powerdown debug registers do not trap to EL3. 528 * 529 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 530 * debug registers, other than those registers that are controlled by 531 * MDCR_EL3.TDOSA. 532 */ 533 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 534 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 535 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 536 537 /* 538 * Configure MDCR_EL3 register as applicable for each world 539 * (NS/Secure/Realm) context. 540 */ 541 manage_extensions_common(ctx); 542 543 /* 544 * Store the X0-X7 value from the entrypoint into the context 545 * Use memcpy as we are in control of the layout of the structures 546 */ 547 gp_regs = get_gpregs_ctx(ctx); 548 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 549 } 550 551 /******************************************************************************* 552 * Context management library initialization routine. This library is used by 553 * runtime services to share pointers to 'cpu_context' structures for secure 554 * non-secure and realm states. Management of the structures and their associated 555 * memory is not done by the context management library e.g. the PSCI service 556 * manages the cpu context used for entry from and exit to the non-secure state. 557 * The Secure payload dispatcher service manages the context(s) corresponding to 558 * the secure state. It also uses this library to get access to the non-secure 559 * state cpu context pointers. 560 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 561 * which will be used for programming an entry into a lower EL. The same context 562 * will be used to save state upon exception entry from that EL. 563 ******************************************************************************/ 564 void __init cm_init(void) 565 { 566 /* 567 * The context management library has only global data to initialize, but 568 * that will be done when the BSS is zeroed out. 569 */ 570 } 571 572 /******************************************************************************* 573 * This is the high-level function used to initialize the cpu_context 'ctx' for 574 * first use. It performs initializations that are common to all security states 575 * and initializations specific to the security state specified in 'ep' 576 ******************************************************************************/ 577 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 578 { 579 unsigned int security_state; 580 581 assert(ctx != NULL); 582 583 /* 584 * Perform initializations that are common 585 * to all security states 586 */ 587 setup_context_common(ctx, ep); 588 589 security_state = GET_SECURITY_STATE(ep->h.attr); 590 591 /* Perform security state specific initializations */ 592 switch (security_state) { 593 case SECURE: 594 setup_secure_context(ctx, ep); 595 break; 596 #if ENABLE_RME 597 case REALM: 598 setup_realm_context(ctx, ep); 599 break; 600 #endif 601 case NON_SECURE: 602 setup_ns_context(ctx, ep); 603 break; 604 default: 605 ERROR("Invalid security state\n"); 606 panic(); 607 break; 608 } 609 } 610 611 /******************************************************************************* 612 * Enable architecture extensions for EL3 execution. This function only updates 613 * registers in-place which are expected to either never change or be 614 * overwritten by el3_exit. 615 ******************************************************************************/ 616 #if IMAGE_BL31 617 void cm_manage_extensions_el3(void) 618 { 619 if (is_feat_amu_supported()) { 620 amu_init_el3(); 621 } 622 623 if (is_feat_sme_supported()) { 624 sme_init_el3(); 625 } 626 627 pmuv3_init_el3(); 628 } 629 #endif /* IMAGE_BL31 */ 630 631 /****************************************************************************** 632 * Function to initialise the registers with the RESET values in the context 633 * memory, which are maintained per world. 634 ******************************************************************************/ 635 #if IMAGE_BL31 636 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 637 { 638 /* 639 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 640 * 641 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 642 * by Advanced SIMD, floating-point or SVE instructions (if 643 * implemented) do not trap to EL3. 644 * 645 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 646 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 647 */ 648 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 649 650 per_world_ctx->ctx_cptr_el3 = cptr_el3; 651 652 /* 653 * Initialize MPAM3_EL3 to its default reset value 654 * 655 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 656 * all lower ELn MPAM3_EL3 register access to, trap to EL3 657 */ 658 659 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 660 } 661 #endif /* IMAGE_BL31 */ 662 663 /******************************************************************************* 664 * Initialise per_world_context for Non-Secure world. 665 * This function enables the architecture extensions, which have same value 666 * across the cores for the non-secure world. 667 ******************************************************************************/ 668 #if IMAGE_BL31 669 void manage_extensions_nonsecure_per_world(void) 670 { 671 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 672 673 if (is_feat_sme_supported()) { 674 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 675 } 676 677 if (is_feat_sve_supported()) { 678 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 679 } 680 681 if (is_feat_amu_supported()) { 682 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 683 } 684 685 if (is_feat_sys_reg_trace_supported()) { 686 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 687 } 688 689 if (is_feat_mpam_supported()) { 690 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 691 } 692 } 693 #endif /* IMAGE_BL31 */ 694 695 /******************************************************************************* 696 * Initialise per_world_context for Secure world. 697 * This function enables the architecture extensions, which have same value 698 * across the cores for the secure world. 699 ******************************************************************************/ 700 static void manage_extensions_secure_per_world(void) 701 { 702 #if IMAGE_BL31 703 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 704 705 if (is_feat_sme_supported()) { 706 707 if (ENABLE_SME_FOR_SWD) { 708 /* 709 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 710 * SME, SVE, and FPU/SIMD context properly managed. 711 */ 712 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 713 } else { 714 /* 715 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 716 * world can safely use the associated registers. 717 */ 718 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 719 } 720 } 721 if (is_feat_sve_supported()) { 722 if (ENABLE_SVE_FOR_SWD) { 723 /* 724 * Enable SVE and FPU in secure context, SPM must ensure 725 * that the SVE and FPU register contexts are properly managed. 726 */ 727 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 728 } else { 729 /* 730 * Disable SVE and FPU in secure context so non-secure world 731 * can safely use them. 732 */ 733 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 734 } 735 } 736 737 /* NS can access this but Secure shouldn't */ 738 if (is_feat_sys_reg_trace_supported()) { 739 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 740 } 741 742 has_secure_perworld_init = true; 743 #endif /* IMAGE_BL31 */ 744 } 745 746 /******************************************************************************* 747 * Enable architecture extensions on first entry to Non-secure world only 748 * and disable for secure world. 749 * 750 * NOTE: Arch features which have been provided with the capability of getting 751 * enabled only for non-secure world and being disabled for secure world are 752 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 753 ******************************************************************************/ 754 static void manage_extensions_common(cpu_context_t *ctx) 755 { 756 #if IMAGE_BL31 757 if (is_feat_spe_supported()) { 758 /* 759 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 760 */ 761 spe_enable(ctx); 762 } 763 764 if (is_feat_trbe_supported()) { 765 /* 766 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 767 * Realm state. 768 */ 769 trbe_enable(ctx); 770 } 771 772 if (is_feat_trf_supported()) { 773 /* 774 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 775 */ 776 trf_enable(ctx); 777 } 778 #endif /* IMAGE_BL31 */ 779 } 780 781 /******************************************************************************* 782 * Enable architecture extensions on first entry to Non-secure world. 783 ******************************************************************************/ 784 static void manage_extensions_nonsecure(cpu_context_t *ctx) 785 { 786 #if IMAGE_BL31 787 if (is_feat_amu_supported()) { 788 amu_enable(ctx); 789 } 790 791 if (is_feat_sme_supported()) { 792 sme_enable(ctx); 793 } 794 795 if (is_feat_fgt2_supported()) { 796 fgt2_enable(ctx); 797 } 798 799 if (is_feat_debugv8p9_supported()) { 800 debugv8p9_extended_bp_wp_enable(ctx); 801 } 802 803 if (is_feat_brbe_supported()) { 804 brbe_enable(ctx); 805 } 806 807 pmuv3_enable(ctx); 808 #endif /* IMAGE_BL31 */ 809 } 810 811 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 812 static __unused void enable_pauth_el2(void) 813 { 814 u_register_t hcr_el2 = read_hcr_el2(); 815 /* 816 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 817 * accessing key registers or using pointer authentication instructions 818 * from lower ELs. 819 */ 820 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 821 822 write_hcr_el2(hcr_el2); 823 } 824 825 #if INIT_UNUSED_NS_EL2 826 /******************************************************************************* 827 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 828 * world when EL2 is empty and unused. 829 ******************************************************************************/ 830 static void manage_extensions_nonsecure_el2_unused(void) 831 { 832 #if IMAGE_BL31 833 if (is_feat_spe_supported()) { 834 spe_init_el2_unused(); 835 } 836 837 if (is_feat_amu_supported()) { 838 amu_init_el2_unused(); 839 } 840 841 if (is_feat_mpam_supported()) { 842 mpam_init_el2_unused(); 843 } 844 845 if (is_feat_trbe_supported()) { 846 trbe_init_el2_unused(); 847 } 848 849 if (is_feat_sys_reg_trace_supported()) { 850 sys_reg_trace_init_el2_unused(); 851 } 852 853 if (is_feat_trf_supported()) { 854 trf_init_el2_unused(); 855 } 856 857 pmuv3_init_el2_unused(); 858 859 if (is_feat_sve_supported()) { 860 sve_init_el2_unused(); 861 } 862 863 if (is_feat_sme_supported()) { 864 sme_init_el2_unused(); 865 } 866 867 #if ENABLE_PAUTH 868 enable_pauth_el2(); 869 #endif /* ENABLE_PAUTH */ 870 #endif /* IMAGE_BL31 */ 871 } 872 #endif /* INIT_UNUSED_NS_EL2 */ 873 874 /******************************************************************************* 875 * Enable architecture extensions on first entry to Secure world. 876 ******************************************************************************/ 877 static void manage_extensions_secure(cpu_context_t *ctx) 878 { 879 #if IMAGE_BL31 880 if (is_feat_sme_supported()) { 881 if (ENABLE_SME_FOR_SWD) { 882 /* 883 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 884 * must ensure SME, SVE, and FPU/SIMD context properly managed. 885 */ 886 sme_init_el3(); 887 sme_enable(ctx); 888 } else { 889 /* 890 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 891 * world can safely use the associated registers. 892 */ 893 sme_disable(ctx); 894 } 895 } 896 #endif /* IMAGE_BL31 */ 897 } 898 899 #if !IMAGE_BL1 900 /******************************************************************************* 901 * The following function initializes the cpu_context for a CPU specified by 902 * its `cpu_idx` for first use, and sets the initial entrypoint state as 903 * specified by the entry_point_info structure. 904 ******************************************************************************/ 905 void cm_init_context_by_index(unsigned int cpu_idx, 906 const entry_point_info_t *ep) 907 { 908 cpu_context_t *ctx; 909 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 910 cm_setup_context(ctx, ep); 911 } 912 #endif /* !IMAGE_BL1 */ 913 914 /******************************************************************************* 915 * The following function initializes the cpu_context for the current CPU 916 * for first use, and sets the initial entrypoint state as specified by the 917 * entry_point_info structure. 918 ******************************************************************************/ 919 void cm_init_my_context(const entry_point_info_t *ep) 920 { 921 cpu_context_t *ctx; 922 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 923 cm_setup_context(ctx, ep); 924 } 925 926 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 927 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 928 { 929 #if INIT_UNUSED_NS_EL2 930 u_register_t hcr_el2 = HCR_RESET_VAL; 931 u_register_t mdcr_el2; 932 u_register_t scr_el3; 933 934 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 935 936 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 937 if ((scr_el3 & SCR_RW_BIT) != 0U) { 938 hcr_el2 |= HCR_RW_BIT; 939 } 940 941 write_hcr_el2(hcr_el2); 942 943 /* 944 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 945 * All fields have architecturally UNKNOWN reset values. 946 */ 947 write_cptr_el2(CPTR_EL2_RESET_VAL); 948 949 /* 950 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 951 * reset and are set to zero except for field(s) listed below. 952 * 953 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 954 * Non-secure EL0 and EL1 accesses to the physical timer registers. 955 * 956 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 957 * Non-secure EL0 and EL1 accesses to the physical counter registers. 958 */ 959 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 960 961 /* 962 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 963 * UNKNOWN value. 964 */ 965 write_cntvoff_el2(0); 966 967 /* 968 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 969 * respectively. 970 */ 971 write_vpidr_el2(read_midr_el1()); 972 write_vmpidr_el2(read_mpidr_el1()); 973 974 /* 975 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 976 * 977 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 978 * translation is disabled, cache maintenance operations depend on the 979 * VMID. 980 * 981 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 982 * disabled. 983 */ 984 write_vttbr_el2(VTTBR_RESET_VAL & 985 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 986 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 987 988 /* 989 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 990 * Some fields are architecturally UNKNOWN on reset. 991 * 992 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 993 * register accesses to the Debug ROM registers are not trapped to EL2. 994 * 995 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 996 * accesses to the powerdown debug registers are not trapped to EL2. 997 * 998 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 999 * debug registers do not trap to EL2. 1000 * 1001 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1002 * EL2. 1003 */ 1004 mdcr_el2 = MDCR_EL2_RESET_VAL & 1005 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1006 MDCR_EL2_TDE_BIT); 1007 1008 write_mdcr_el2(mdcr_el2); 1009 1010 /* 1011 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1012 * 1013 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1014 * EL1 accesses to System registers do not trap to EL2. 1015 */ 1016 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1017 1018 /* 1019 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1020 * reset. 1021 * 1022 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1023 * and prevent timer interrupts. 1024 */ 1025 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1026 1027 manage_extensions_nonsecure_el2_unused(); 1028 #endif /* INIT_UNUSED_NS_EL2 */ 1029 } 1030 1031 /******************************************************************************* 1032 * Prepare the CPU system registers for first entry into realm, secure, or 1033 * normal world. 1034 * 1035 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1036 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1037 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1038 * For all entries, the EL1 registers are initialized from the cpu_context 1039 ******************************************************************************/ 1040 void cm_prepare_el3_exit(uint32_t security_state) 1041 { 1042 u_register_t sctlr_el2, scr_el3; 1043 cpu_context_t *ctx = cm_get_context(security_state); 1044 1045 assert(ctx != NULL); 1046 1047 if (security_state == NON_SECURE) { 1048 uint64_t el2_implemented = el_implemented(2); 1049 1050 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1051 CTX_SCR_EL3); 1052 1053 if (el2_implemented != EL_IMPL_NONE) { 1054 1055 /* 1056 * If context is not being used for EL2, initialize 1057 * HCRX_EL2 with its init value here. 1058 */ 1059 if (is_feat_hcx_supported()) { 1060 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1061 } 1062 1063 /* 1064 * Initialize Fine-grained trap registers introduced 1065 * by FEAT_FGT so all traps are initially disabled when 1066 * switching to EL2 or a lower EL, preventing undesired 1067 * behavior. 1068 */ 1069 if (is_feat_fgt_supported()) { 1070 /* 1071 * Initialize HFG*_EL2 registers with a default 1072 * value so legacy systems unaware of FEAT_FGT 1073 * do not get trapped due to their lack of 1074 * initialization for this feature. 1075 */ 1076 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1077 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1078 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1079 } 1080 1081 /* Condition to ensure EL2 is being used. */ 1082 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1083 /* Initialize SCTLR_EL2 register with reset value. */ 1084 sctlr_el2 = SCTLR_EL2_RES1; 1085 1086 /* 1087 * If workaround of errata 764081 for Cortex-A75 1088 * is used then set SCTLR_EL2.IESB to enable 1089 * Implicit Error Synchronization Barrier. 1090 */ 1091 if (errata_a75_764081_applies()) { 1092 sctlr_el2 |= SCTLR_IESB_BIT; 1093 } 1094 1095 write_sctlr_el2(sctlr_el2); 1096 } else { 1097 /* 1098 * (scr_el3 & SCR_HCE_BIT==0) 1099 * EL2 implemented but unused. 1100 */ 1101 init_nonsecure_el2_unused(ctx); 1102 } 1103 } 1104 } 1105 #if (!CTX_INCLUDE_EL2_REGS) 1106 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1107 cm_el1_sysregs_context_restore(security_state); 1108 #endif 1109 cm_set_next_eret_context(security_state); 1110 } 1111 1112 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1113 1114 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1115 { 1116 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1117 if (is_feat_amu_supported()) { 1118 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1119 } 1120 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1121 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1122 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1123 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1124 } 1125 1126 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1127 { 1128 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1129 if (is_feat_amu_supported()) { 1130 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1131 } 1132 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1133 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1134 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1135 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1136 } 1137 1138 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1139 { 1140 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1141 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1142 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1143 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1144 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1145 } 1146 1147 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1148 { 1149 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1150 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1151 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1152 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1153 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1154 } 1155 1156 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1157 { 1158 u_register_t mpam_idr = read_mpamidr_el1(); 1159 1160 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1161 1162 /* 1163 * The context registers that we intend to save would be part of the 1164 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1165 */ 1166 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1167 return; 1168 } 1169 1170 /* 1171 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1172 * MPAMIDR_HAS_HCR_BIT == 1. 1173 */ 1174 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1175 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1176 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1177 1178 /* 1179 * The number of MPAMVPM registers is implementation defined, their 1180 * number is stored in the MPAMIDR_EL1 register. 1181 */ 1182 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1183 case 7: 1184 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1185 __fallthrough; 1186 case 6: 1187 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1188 __fallthrough; 1189 case 5: 1190 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1191 __fallthrough; 1192 case 4: 1193 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1194 __fallthrough; 1195 case 3: 1196 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1197 __fallthrough; 1198 case 2: 1199 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1200 __fallthrough; 1201 case 1: 1202 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1203 break; 1204 } 1205 } 1206 1207 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1208 { 1209 u_register_t mpam_idr = read_mpamidr_el1(); 1210 1211 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1212 1213 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1214 return; 1215 } 1216 1217 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1218 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1219 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1220 1221 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1222 case 7: 1223 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1224 __fallthrough; 1225 case 6: 1226 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1227 __fallthrough; 1228 case 5: 1229 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1230 __fallthrough; 1231 case 4: 1232 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1233 __fallthrough; 1234 case 3: 1235 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1236 __fallthrough; 1237 case 2: 1238 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1239 __fallthrough; 1240 case 1: 1241 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1242 break; 1243 } 1244 } 1245 1246 /* --------------------------------------------------------------------------- 1247 * The following registers are not added: 1248 * ICH_AP0R<n>_EL2 1249 * ICH_AP1R<n>_EL2 1250 * ICH_LR<n>_EL2 1251 * 1252 * NOTE: For a system with S-EL2 present but not enabled, accessing 1253 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1254 * SCR_EL3.NS = 1 before accessing this register. 1255 * --------------------------------------------------------------------------- 1256 */ 1257 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1258 { 1259 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1260 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1261 #else 1262 u_register_t scr_el3 = read_scr_el3(); 1263 write_scr_el3(scr_el3 | SCR_NS_BIT); 1264 isb(); 1265 1266 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1267 1268 write_scr_el3(scr_el3); 1269 isb(); 1270 #endif 1271 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1272 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1273 } 1274 1275 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1276 { 1277 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1278 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1279 #else 1280 u_register_t scr_el3 = read_scr_el3(); 1281 write_scr_el3(scr_el3 | SCR_NS_BIT); 1282 isb(); 1283 1284 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1285 1286 write_scr_el3(scr_el3); 1287 isb(); 1288 #endif 1289 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1290 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1291 } 1292 1293 /* ----------------------------------------------------- 1294 * The following registers are not added: 1295 * AMEVCNTVOFF0<n>_EL2 1296 * AMEVCNTVOFF1<n>_EL2 1297 * ----------------------------------------------------- 1298 */ 1299 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1300 { 1301 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1302 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1303 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1304 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1305 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1306 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1307 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1308 if (CTX_INCLUDE_AARCH32_REGS) { 1309 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1310 } 1311 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1312 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1313 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1314 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1315 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1316 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1317 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1318 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1319 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1320 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1321 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1322 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1323 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1324 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1325 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2()); 1326 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1327 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1328 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1329 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1330 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2()); 1331 } 1332 1333 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1334 { 1335 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1336 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1337 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1338 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1339 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1340 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1341 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1342 if (CTX_INCLUDE_AARCH32_REGS) { 1343 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1344 } 1345 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1346 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1347 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1348 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1349 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1350 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1351 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1352 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1353 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1354 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1355 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1356 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1357 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1358 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1359 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1360 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1361 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1362 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1363 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1364 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1365 } 1366 1367 /******************************************************************************* 1368 * Save EL2 sysreg context 1369 ******************************************************************************/ 1370 void cm_el2_sysregs_context_save(uint32_t security_state) 1371 { 1372 cpu_context_t *ctx; 1373 el2_sysregs_t *el2_sysregs_ctx; 1374 1375 ctx = cm_get_context(security_state); 1376 assert(ctx != NULL); 1377 1378 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1379 1380 el2_sysregs_context_save_common(el2_sysregs_ctx); 1381 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1382 1383 if (is_feat_mte2_supported()) { 1384 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1385 } 1386 1387 if (is_feat_mpam_supported()) { 1388 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1389 } 1390 1391 if (is_feat_fgt_supported()) { 1392 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1393 } 1394 1395 if (is_feat_fgt2_supported()) { 1396 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1397 } 1398 1399 if (is_feat_ecv_v2_supported()) { 1400 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1401 } 1402 1403 if (is_feat_vhe_supported()) { 1404 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1405 read_contextidr_el2()); 1406 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1407 } 1408 1409 if (is_feat_ras_supported()) { 1410 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1411 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1412 } 1413 1414 if (is_feat_nv2_supported()) { 1415 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1416 } 1417 1418 if (is_feat_trf_supported()) { 1419 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1420 } 1421 1422 if (is_feat_csv2_2_supported()) { 1423 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1424 read_scxtnum_el2()); 1425 } 1426 1427 if (is_feat_hcx_supported()) { 1428 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1429 } 1430 1431 if (is_feat_tcr2_supported()) { 1432 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1433 } 1434 1435 if (is_feat_sxpie_supported()) { 1436 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1437 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1438 } 1439 1440 if (is_feat_sxpoe_supported()) { 1441 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1442 } 1443 1444 if (is_feat_s2pie_supported()) { 1445 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1446 } 1447 1448 if (is_feat_gcs_supported()) { 1449 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1450 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1451 } 1452 1453 if (is_feat_sctlr2_supported()) { 1454 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1455 } 1456 } 1457 1458 /******************************************************************************* 1459 * Restore EL2 sysreg context 1460 ******************************************************************************/ 1461 void cm_el2_sysregs_context_restore(uint32_t security_state) 1462 { 1463 cpu_context_t *ctx; 1464 el2_sysregs_t *el2_sysregs_ctx; 1465 1466 ctx = cm_get_context(security_state); 1467 assert(ctx != NULL); 1468 1469 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1470 1471 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1472 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1473 1474 if (is_feat_mte2_supported()) { 1475 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1476 } 1477 1478 if (is_feat_mpam_supported()) { 1479 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1480 } 1481 1482 if (is_feat_fgt_supported()) { 1483 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1484 } 1485 1486 if (is_feat_fgt2_supported()) { 1487 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1488 } 1489 1490 if (is_feat_ecv_v2_supported()) { 1491 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1492 } 1493 1494 if (is_feat_vhe_supported()) { 1495 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1496 contextidr_el2)); 1497 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1498 } 1499 1500 if (is_feat_ras_supported()) { 1501 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1502 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1503 } 1504 1505 if (is_feat_nv2_supported()) { 1506 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1507 } 1508 1509 if (is_feat_trf_supported()) { 1510 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1511 } 1512 1513 if (is_feat_csv2_2_supported()) { 1514 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1515 scxtnum_el2)); 1516 } 1517 1518 if (is_feat_hcx_supported()) { 1519 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1520 } 1521 1522 if (is_feat_tcr2_supported()) { 1523 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1524 } 1525 1526 if (is_feat_sxpie_supported()) { 1527 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1528 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1529 } 1530 1531 if (is_feat_sxpoe_supported()) { 1532 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1533 } 1534 1535 if (is_feat_s2pie_supported()) { 1536 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1537 } 1538 1539 if (is_feat_gcs_supported()) { 1540 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1541 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1542 } 1543 1544 if (is_feat_sctlr2_supported()) { 1545 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1546 } 1547 } 1548 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1549 1550 #if IMAGE_BL31 1551 /********************************************************************************* 1552 * This function allows Architecture features asymmetry among cores. 1553 * TF-A assumes that all the cores in the platform has architecture feature parity 1554 * and hence the context is setup on different core (e.g. primary sets up the 1555 * context for secondary cores).This assumption may not be true for systems where 1556 * cores are not conforming to same Arch version or there is CPU Erratum which 1557 * requires certain feature to be be disabled only on a given core. 1558 * 1559 * This function is called on secondary cores to override any disparity in context 1560 * setup by primary, this would be called during warmboot path. 1561 *********************************************************************************/ 1562 void cm_handle_asymmetric_features(void) 1563 { 1564 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1565 1566 assert(ctx != NULL); 1567 1568 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1569 if (is_feat_spe_supported()) { 1570 spe_enable(ctx); 1571 } else { 1572 spe_disable(ctx); 1573 } 1574 #endif 1575 1576 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1577 if (check_if_affected_core() == ERRATA_APPLIES) { 1578 if (is_feat_trbe_supported()) { 1579 trbe_disable(ctx); 1580 } 1581 } 1582 #endif 1583 1584 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1585 el3_state_t *el3_state = get_el3state_ctx(ctx); 1586 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1587 1588 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1589 tcr2_enable(ctx); 1590 } else { 1591 tcr2_disable(ctx); 1592 } 1593 #endif 1594 1595 } 1596 #endif 1597 1598 /******************************************************************************* 1599 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1600 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1601 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1602 * cm_prepare_el3_exit function. 1603 ******************************************************************************/ 1604 void cm_prepare_el3_exit_ns(void) 1605 { 1606 #if IMAGE_BL31 1607 /* 1608 * Check and handle Architecture feature asymmetry among cores. 1609 * 1610 * In warmboot path secondary cores context is initialized on core which 1611 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1612 * it in this function call. 1613 * For Symmetric cores this is an empty function. 1614 */ 1615 cm_handle_asymmetric_features(); 1616 #endif 1617 1618 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1619 #if ENABLE_ASSERTIONS 1620 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1621 assert(ctx != NULL); 1622 1623 /* Assert that EL2 is used. */ 1624 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1625 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1626 (el_implemented(2U) != EL_IMPL_NONE)); 1627 #endif /* ENABLE_ASSERTIONS */ 1628 1629 /* Restore EL2 sysreg contexts */ 1630 cm_el2_sysregs_context_restore(NON_SECURE); 1631 cm_set_next_eret_context(NON_SECURE); 1632 #else 1633 cm_prepare_el3_exit(NON_SECURE); 1634 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1635 } 1636 1637 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1638 /******************************************************************************* 1639 * The next set of six functions are used by runtime services to save and restore 1640 * EL1 context on the 'cpu_context' structure for the specified security state. 1641 ******************************************************************************/ 1642 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1643 { 1644 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1645 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1646 1647 #if (!ERRATA_SPECULATIVE_AT) 1648 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1649 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1650 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1651 1652 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1653 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1654 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1655 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1656 write_el1_ctx_common(ctx, ttbr0_el1, read_ttbr0_el1()); 1657 write_el1_ctx_common(ctx, ttbr1_el1, read_ttbr1_el1()); 1658 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1659 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1660 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1661 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1662 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1663 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1664 write_el1_ctx_common(ctx, par_el1, read_par_el1()); 1665 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1666 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1667 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1668 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1669 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1670 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1671 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1672 1673 if (CTX_INCLUDE_AARCH32_REGS) { 1674 /* Save Aarch32 registers */ 1675 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1676 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1677 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1678 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1679 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1680 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1681 } 1682 1683 if (NS_TIMER_SWITCH) { 1684 /* Save NS Timer registers */ 1685 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1686 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1687 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1688 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1689 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1690 } 1691 1692 if (is_feat_mte2_supported()) { 1693 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1694 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1695 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1696 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1697 } 1698 1699 if (is_feat_ras_supported()) { 1700 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1701 } 1702 1703 if (is_feat_s1pie_supported()) { 1704 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1705 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1706 } 1707 1708 if (is_feat_s1poe_supported()) { 1709 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1710 } 1711 1712 if (is_feat_s2poe_supported()) { 1713 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1714 } 1715 1716 if (is_feat_tcr2_supported()) { 1717 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1718 } 1719 1720 if (is_feat_trf_supported()) { 1721 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1722 } 1723 1724 if (is_feat_csv2_2_supported()) { 1725 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1726 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1727 } 1728 1729 if (is_feat_gcs_supported()) { 1730 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1731 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1732 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1733 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1734 } 1735 1736 if (is_feat_the_supported()) { 1737 write_el1_ctx_the(ctx, rcwmask_el1, read_rcwmask_el1()); 1738 write_el1_ctx_the(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1739 } 1740 1741 if (is_feat_sctlr2_supported()) { 1742 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1743 } 1744 1745 } 1746 1747 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1748 { 1749 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1750 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1751 1752 #if (!ERRATA_SPECULATIVE_AT) 1753 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1754 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1755 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1756 1757 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1758 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1759 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1760 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1761 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1762 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1763 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1764 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1765 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1766 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1767 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1768 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1769 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1770 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1771 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1772 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1773 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1774 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1775 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1776 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1777 1778 if (CTX_INCLUDE_AARCH32_REGS) { 1779 /* Restore Aarch32 registers */ 1780 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1781 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1782 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1783 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1784 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1785 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1786 } 1787 1788 if (NS_TIMER_SWITCH) { 1789 /* Restore NS Timer registers */ 1790 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1791 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1792 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1793 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1794 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1795 } 1796 1797 if (is_feat_mte2_supported()) { 1798 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1799 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1800 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1801 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1802 } 1803 1804 if (is_feat_ras_supported()) { 1805 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1806 } 1807 1808 if (is_feat_s1pie_supported()) { 1809 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1810 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1811 } 1812 1813 if (is_feat_s1poe_supported()) { 1814 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1815 } 1816 1817 if (is_feat_s2poe_supported()) { 1818 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1819 } 1820 1821 if (is_feat_tcr2_supported()) { 1822 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1823 } 1824 1825 if (is_feat_trf_supported()) { 1826 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1827 } 1828 1829 if (is_feat_csv2_2_supported()) { 1830 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1831 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1832 } 1833 1834 if (is_feat_gcs_supported()) { 1835 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1836 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1837 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1838 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1839 } 1840 1841 if (is_feat_the_supported()) { 1842 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1843 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1844 } 1845 1846 if (is_feat_sctlr2_supported()) { 1847 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1848 } 1849 1850 } 1851 1852 /******************************************************************************* 1853 * The next couple of functions are used by runtime services to save and restore 1854 * EL1 context on the 'cpu_context' structure for the specified security state. 1855 ******************************************************************************/ 1856 void cm_el1_sysregs_context_save(uint32_t security_state) 1857 { 1858 cpu_context_t *ctx; 1859 1860 ctx = cm_get_context(security_state); 1861 assert(ctx != NULL); 1862 1863 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1864 1865 #if IMAGE_BL31 1866 if (security_state == SECURE) 1867 PUBLISH_EVENT(cm_exited_secure_world); 1868 else 1869 PUBLISH_EVENT(cm_exited_normal_world); 1870 #endif 1871 } 1872 1873 void cm_el1_sysregs_context_restore(uint32_t security_state) 1874 { 1875 cpu_context_t *ctx; 1876 1877 ctx = cm_get_context(security_state); 1878 assert(ctx != NULL); 1879 1880 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1881 1882 #if IMAGE_BL31 1883 if (security_state == SECURE) 1884 PUBLISH_EVENT(cm_entering_secure_world); 1885 else 1886 PUBLISH_EVENT(cm_entering_normal_world); 1887 #endif 1888 } 1889 1890 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1891 1892 /******************************************************************************* 1893 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1894 * given security state with the given entrypoint 1895 ******************************************************************************/ 1896 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1897 { 1898 cpu_context_t *ctx; 1899 el3_state_t *state; 1900 1901 ctx = cm_get_context(security_state); 1902 assert(ctx != NULL); 1903 1904 /* Populate EL3 state so that ERET jumps to the correct entry */ 1905 state = get_el3state_ctx(ctx); 1906 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1907 } 1908 1909 /******************************************************************************* 1910 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1911 * pertaining to the given security state 1912 ******************************************************************************/ 1913 void cm_set_elr_spsr_el3(uint32_t security_state, 1914 uintptr_t entrypoint, uint32_t spsr) 1915 { 1916 cpu_context_t *ctx; 1917 el3_state_t *state; 1918 1919 ctx = cm_get_context(security_state); 1920 assert(ctx != NULL); 1921 1922 /* Populate EL3 state so that ERET jumps to the correct entry */ 1923 state = get_el3state_ctx(ctx); 1924 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1925 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1926 } 1927 1928 /******************************************************************************* 1929 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1930 * pertaining to the given security state using the value and bit position 1931 * specified in the parameters. It preserves all other bits. 1932 ******************************************************************************/ 1933 void cm_write_scr_el3_bit(uint32_t security_state, 1934 uint32_t bit_pos, 1935 uint32_t value) 1936 { 1937 cpu_context_t *ctx; 1938 el3_state_t *state; 1939 u_register_t scr_el3; 1940 1941 ctx = cm_get_context(security_state); 1942 assert(ctx != NULL); 1943 1944 /* Ensure that the bit position is a valid one */ 1945 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1946 1947 /* Ensure that the 'value' is only a bit wide */ 1948 assert(value <= 1U); 1949 1950 /* 1951 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1952 * and set it to its new value. 1953 */ 1954 state = get_el3state_ctx(ctx); 1955 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1956 scr_el3 &= ~(1UL << bit_pos); 1957 scr_el3 |= (u_register_t)value << bit_pos; 1958 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1959 } 1960 1961 /******************************************************************************* 1962 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1963 * given security state. 1964 ******************************************************************************/ 1965 u_register_t cm_get_scr_el3(uint32_t security_state) 1966 { 1967 cpu_context_t *ctx; 1968 el3_state_t *state; 1969 1970 ctx = cm_get_context(security_state); 1971 assert(ctx != NULL); 1972 1973 /* Populate EL3 state so that ERET jumps to the correct entry */ 1974 state = get_el3state_ctx(ctx); 1975 return read_ctx_reg(state, CTX_SCR_EL3); 1976 } 1977 1978 /******************************************************************************* 1979 * This function is used to program the context that's used for exception 1980 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1981 * the required security state 1982 ******************************************************************************/ 1983 void cm_set_next_eret_context(uint32_t security_state) 1984 { 1985 cpu_context_t *ctx; 1986 1987 ctx = cm_get_context(security_state); 1988 assert(ctx != NULL); 1989 1990 cm_set_next_context(ctx); 1991 } 1992