1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLAT_SOCFPGA_DEF_H 10 #define PLAT_SOCFPGA_DEF_H 11 12 #include "agilex5_memory_controller.h" 13 #include "agilex5_system_manager.h" 14 15 #include <platform_def.h> 16 17 /* Platform Setting */ 18 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 19 /* 1 = Flush cache, 0 = No cache flush. 20 * Default for Agilex5 is Cache flush. 21 */ 22 #define CACHE_FLUSH 1 23 #define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */ 24 #define XLAT_TABLES_V2 U(1) 25 #define PLAT_PRIMARY_CPU_A55 0x000 26 #define PLAT_PRIMARY_CPU_A76 0x200 27 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT 28 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 29 #define PLAT_L2_RESET_REQ 0xB007C0DE 30 #define PLAT_TIMER_BASE_ADDR 0x10D01000 31 32 /* System Counter */ 33 /* TODO: Update back to 400MHz. 34 * This shall be updated to read from L4 clock instead of hardcoded. 35 */ 36 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS U(400000000) 37 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 38 39 /* FPGA config helpers */ 40 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x80400000 41 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x82000000 42 43 /* QSPI Setting */ 44 #define CAD_QSPIDATA_OFST 0x10900000 45 #define CAD_QSPI_OFFSET 0x108d2000 46 47 /* SDMMC Setting */ 48 # if ARM_LINUX_KERNEL_AS_BL33 49 #define SOCFPGA_MMC_BLOCK_SIZE U(32768) 50 # else 51 #define SOCFPGA_MMC_BLOCK_SIZE U(8192) 52 # endif 53 54 /* Register Mapping */ 55 #define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000 56 #define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000 57 58 #define SOCFPGA_MMC_REG_BASE 0x10808000 59 #define SOCFPGA_MEMCTRL_REG_BASE 0x108CC000 60 #define SOCFPGA_RSTMGR_REG_BASE 0x10d11000 61 #define SOCFPGA_SYSMGR_REG_BASE 0x10d12000 62 #define SOCFPGA_PINMUX_REG_BASE 0x10d13000 63 #define SOCFPGA_NAND_REG_BASE 0x10B80000 64 #define SOCFPGA_ECC_QSPI_REG_BASE 0x10A22000 65 66 #define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000 67 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100 68 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200 69 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300 70 71 /* Define maximum page size for NAND flash devices */ 72 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x2000) 73 74 /******************************************************************************* 75 * Platform memory map related constants 76 ******************************************************************************/ 77 #define DRAM_BASE (0x80000000) 78 #define DRAM_SIZE (0x80000000) 79 80 #define OCRAM_BASE (0x00000000) 81 #define OCRAM_SIZE (0x00080000) 82 83 #define MEM64_BASE (0x0080000000) 84 #define MEM64_SIZE (0x0080000000) 85 86 //128MB PSS 87 #define PSS_BASE (0x10000000) 88 #define PSS_SIZE (0x08000000) 89 90 //64MB MPFE 91 #define MPFE_BASE (0x18000000) 92 #define MPFE_SIZE (0x04000000) 93 94 //16MB CCU 95 #define CCU_BASE (0x1C000000) 96 #define CCU_SIZE (0x01000000) 97 98 //1MB GIC 99 #define GIC_BASE (0x1D000000) 100 #define GIC_SIZE (0x00100000) 101 102 #define BL2_BASE (0x00000000) 103 #define BL2_LIMIT (0x0007E000) 104 105 #define BL31_BASE (0x80000000) 106 #define BL31_LIMIT (0x82000000) 107 /******************************************************************************* 108 * UART related constants 109 ******************************************************************************/ 110 #define PLAT_UART0_BASE (0x10C02000) 111 #define PLAT_UART1_BASE (0x10C02100) 112 113 /******************************************************************************* 114 * WDT related constants 115 ******************************************************************************/ 116 #define WDT_BASE (0x10D00200) 117 118 /******************************************************************************* 119 * GIC related constants 120 ******************************************************************************/ 121 #define PLAT_GIC_BASE (0x1D000000) 122 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x20000) 123 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x00000) 124 #define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x60000) 125 126 #define PLAT_INTEL_SOCFPGA_GICR_BASE PLAT_GICR_BASE 127 128 /******************************************************************************* 129 * SDMMC related pointer function 130 ******************************************************************************/ 131 #define SDMMC_READ_BLOCKS sdmmc_read_blocks 132 #define SDMMC_WRITE_BLOCKS sdmmc_write_blocks 133 134 /******************************************************************************* 135 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 136 * is done and HPS should trigger warm reset via RMR_EL3. 137 ******************************************************************************/ 138 #define L2_RESET_DONE_REG 0x10D12218 139 140 #endif /* PLAT_SOCFPGA_DEF_H */ 141