1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLAT_SOCFPGA_DEF_H 10 #define PLAT_SOCFPGA_DEF_H 11 12 #include "agilex_system_manager.h" 13 #include <lib/utils_def.h> 14 #include <platform_def.h> 15 16 /* Platform Setting */ 17 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX 18 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 19 /* 1 = Flush cache, 0 = No cache flush. 20 * Default for Agilex is No cache flush. 21 * For Agilex FP8, set to Flush cache. 22 */ 23 #define CACHE_FLUSH 0 24 #define PLAT_PRIMARY_CPU 0 25 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 26 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT 27 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 28 #define PLAT_TIMER_BASE_ADDR 0xFFD01000 29 30 /* FPGA config helpers */ 31 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 32 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 33 34 /* QSPI Setting */ 35 #define CAD_QSPIDATA_OFST 0xff900000 36 #define CAD_QSPI_OFFSET 0xff8d2000 37 38 /* FIP Setting */ 39 #define PLAT_FIP_BASE (0) 40 #if ARM_LINUX_KERNEL_AS_BL33 41 #define PLAT_FIP_MAX_SIZE (0x8000000) 42 #else 43 #define PLAT_FIP_MAX_SIZE (0x1000000) 44 #endif 45 46 /* SDMMC Setting */ 47 #if ARM_LINUX_KERNEL_AS_BL33 48 #define PLAT_MMC_DATA_BASE (0x10000000) 49 #define PLAT_MMC_DATA_SIZE (0x100000) 50 #define SOCFPGA_MMC_BLOCK_SIZE U(32768) 51 #else 52 #define PLAT_MMC_DATA_BASE (0xffe3c000) 53 #define PLAT_MMC_DATA_SIZE (0x2000 54 #define SOCFPGA_MMC_BLOCK_SIZE U(8192) 55 #endif 56 57 /* Register Mapping */ 58 #define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 59 #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) 60 61 #define SOCFPGA_MMC_REG_BASE 0xff808000 62 #define SOCFPGA_MEMCTRL_REG_BASE 0xf8011100 63 #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 64 #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 65 #define SOCFPGA_ECC_QSPI_REG_BASE 0xffa22000 66 67 #define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 68 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 69 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 70 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 71 72 /******************************************************************************* 73 * Platform memory map related constants 74 ******************************************************************************/ 75 #define DRAM_BASE (0x0) 76 #define DRAM_SIZE (0x80000000) 77 78 #define OCRAM_BASE (0xFFE00000) 79 #define OCRAM_SIZE (0x00040000) 80 81 #define MEM64_BASE (0x0100000000) 82 #define MEM64_SIZE (0x1F00000000) 83 84 #define DEVICE1_BASE (0x80000000) 85 #define DEVICE1_SIZE (0x60000000) 86 87 #define DEVICE2_BASE (0xF7000000) 88 #define DEVICE2_SIZE (0x08E00000) 89 90 #define DEVICE3_BASE (0xFFFC0000) 91 #define DEVICE3_SIZE (0x00008000) 92 93 #define DEVICE4_BASE (0x2000000000) 94 #define DEVICE4_SIZE (0x0100000000) 95 96 #define BL2_BASE (0xffe00000) 97 #define BL2_LIMIT (0xffe2b000) 98 99 #define BL31_BASE (0x1000) 100 #define BL31_LIMIT (0x81000) 101 102 /******************************************************************************* 103 * UART related constants 104 ******************************************************************************/ 105 #define PLAT_UART0_BASE (0xFFC02000) 106 #define PLAT_UART1_BASE (0xFFC02100) 107 108 /******************************************************************************* 109 * WDT related constants 110 ******************************************************************************/ 111 #define WDT_BASE (0xFFD00200) 112 113 /******************************************************************************* 114 * GIC related constants 115 ******************************************************************************/ 116 #define PLAT_GIC_BASE (0xFFFC0000) 117 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 118 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 119 #define PLAT_GICR_BASE 0 120 121 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) 122 #define PLAT_HZ_CONVERT_TO_MHZ (1000000) 123 124 /******************************************************************************* 125 * SDMMC related pointer function 126 ******************************************************************************/ 127 #define SDMMC_READ_BLOCKS sdmmc_read_blocks 128 #define SDMMC_WRITE_BLOCKS mmc_write_blocks 129 130 /******************************************************************************* 131 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 132 * is done and HPS should trigger warm reset via RMR_EL3. 133 ******************************************************************************/ 134 #define L2_RESET_DONE_REG 0xFFD12218 135 136 /* Platform specific system counter */ 137 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 138 139 #endif /* PLAT_SOCFPGA_DEF_H */ 140