1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLAT_SOCFPGA_DEF_H 10 #define PLAT_SOCFPGA_DEF_H 11 12 #include "agilex5_memory_controller.h" 13 #include "agilex5_system_manager.h" 14 15 #include <platform_def.h> 16 17 /* Platform Setting */ 18 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 19 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 20 /* 1 = Flush cache, 0 = No cache flush. 21 * Default for Agilex5 is Cache flush. 22 */ 23 #define CACHE_FLUSH 1 24 #define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */ 25 #define XLAT_TABLES_V2 U(1) 26 #define PLAT_PRIMARY_CPU_A55 0x000 27 #define PLAT_PRIMARY_CPU_A76 0x200 28 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT 29 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 30 #define PLAT_L2_RESET_REQ 0xB007C0DE 31 #define PLAT_HANDOFF_OFFSET 0x0007F000 32 #define PLAT_TIMER_BASE_ADDR 0x10D01000 33 34 /* System Counter */ 35 /* TODO: Update back to 400MHz. 36 * This shall be updated to read from L4 clock instead of hardcoded. 37 */ 38 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS U(400000000) 39 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 40 41 /* FPGA config helpers */ 42 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x80400000 43 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x82000000 44 45 /* QSPI Setting */ 46 #define CAD_QSPIDATA_OFST 0x10900000 47 #define CAD_QSPI_OFFSET 0x108d2000 48 49 /* FIP Setting */ 50 #define PLAT_FIP_BASE (0) 51 #if ARM_LINUX_KERNEL_AS_BL33 52 #define PLAT_FIP_MAX_SIZE (0x8000000) 53 #else 54 #define PLAT_FIP_MAX_SIZE (0x1000000) 55 #endif 56 57 /* SDMMC Setting */ 58 #if ARM_LINUX_KERNEL_AS_BL33 59 #define PLAT_MMC_DATA_BASE (0x90000000) 60 #define PLAT_MMC_DATA_SIZE (0x100000) 61 #define SOCFPGA_MMC_BLOCK_SIZE U(32768) 62 #else 63 #define PLAT_MMC_DATA_BASE (0x0007D000) 64 #define PLAT_MMC_DATA_SIZE (0x2000) 65 #define SOCFPGA_MMC_BLOCK_SIZE U(8192) 66 #endif 67 68 /* Register Mapping */ 69 #define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000 70 #define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000 71 72 #define SOCFPGA_MMC_REG_BASE 0x10808000 73 #define SOCFPGA_MEMCTRL_REG_BASE 0x108CC000 74 #define SOCFPGA_RSTMGR_REG_BASE 0x10d11000 75 #define SOCFPGA_SYSMGR_REG_BASE 0x10d12000 76 #define SOCFPGA_PINMUX_REG_BASE 0x10d13000 77 #define SOCFPGA_NAND_REG_BASE 0x10B80000 78 #define SOCFPGA_ECC_QSPI_REG_BASE 0x10A22000 79 80 #define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000 81 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100 82 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200 83 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300 84 #define SOCFPGA_SDMMC_SECU_BIT 0x40 85 #define SOCFPGA_LWSOC2FPGA_ENABLE 0xffe0301 86 #define SOCFPGA_SDMMC_SECU_BIT_ENABLE 0x1010001 87 88 89 /* Define maximum page size for NAND flash devices */ 90 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x2000) 91 92 /* OCRAM Register*/ 93 94 #define OCRAM_REG_BASE 0x108CC400 95 #define OCRAM_REGION_0_OFFSET 0x18 96 #define OCRAM_REGION_0_REG_BASE (OCRAM_REG_BASE + \ 97 OCRAM_REGION_0_OFFSET) 98 #define OCRAM_NON_SECURE_ENABLE 0x0 99 100 /******************************************************************************* 101 * Platform memory map related constants 102 ******************************************************************************/ 103 #define DRAM_BASE (0x80000000) 104 #define DRAM_SIZE (0x80000000) 105 106 #define OCRAM_BASE (0x00000000) 107 #define OCRAM_SIZE (0x00080000) 108 109 #define MEM64_BASE (0x0080000000) 110 #define MEM64_SIZE (0x0080000000) 111 112 //128MB PSS 113 #define PSS_BASE (0x10000000) 114 #define PSS_SIZE (0x08000000) 115 116 //64MB MPFE 117 #define MPFE_BASE (0x18000000) 118 #define MPFE_SIZE (0x04000000) 119 120 //16MB CCU 121 #define CCU_BASE (0x1C000000) 122 #define CCU_SIZE (0x01000000) 123 124 //1MB GIC 125 #define GIC_BASE (0x1D000000) 126 #define GIC_SIZE (0x00100000) 127 128 #define BL2_BASE (0x00000000) 129 #define BL2_LIMIT (0x0007E000) 130 131 #define BL31_BASE (0x80000000) 132 #define BL31_LIMIT (0x82000000) 133 /******************************************************************************* 134 * UART related constants 135 ******************************************************************************/ 136 #define PLAT_UART0_BASE (0x10C02000) 137 #define PLAT_UART1_BASE (0x10C02100) 138 139 /******************************************************************************* 140 * WDT related constants 141 ******************************************************************************/ 142 #define WDT_BASE (0x10D00200) 143 144 /******************************************************************************* 145 * GIC related constants 146 ******************************************************************************/ 147 #define PLAT_GIC_BASE (0x1D000000) 148 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x20000) 149 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x00000) 150 #define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x60000) 151 152 #define PLAT_INTEL_SOCFPGA_GICR_BASE PLAT_GICR_BASE 153 154 /******************************************************************************* 155 * SDMMC related pointer function 156 ******************************************************************************/ 157 #define SDMMC_READ_BLOCKS sdmmc_read_blocks 158 #define SDMMC_WRITE_BLOCKS sdmmc_write_blocks 159 160 /******************************************************************************* 161 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 162 * is done and HPS should trigger warm reset via RMR_EL3. 163 ******************************************************************************/ 164 #define L2_RESET_DONE_REG 0x10D12218 165 166 #endif /* PLAT_SOCFPGA_DEF_H */ 167