1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2024, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLAT_SOCFPGA_DEF_H 9 #define PLAT_SOCFPGA_DEF_H 10 11 #include <platform_def.h> 12 #include <lib/utils_def.h> 13 #include "s10_system_manager.h" 14 15 /* Platform Setting */ 16 #define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 17 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 18 #define PLAT_PRIMARY_CPU 0 19 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 20 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT 21 #define PLAT_TIMER_BASE_ADDR 0xFFD01000 22 23 /* FPGA config helpers */ 24 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 25 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x1000000 26 27 /* QSPI Setting */ 28 #define CAD_QSPIDATA_OFST 0xff900000 29 #define CAD_QSPI_OFFSET 0xff8d2000 30 31 /* SDMMC Setting */ 32 # if ARM_LINUX_KERNEL_AS_BL33 33 #define SOCFPGA_MMC_BLOCK_SIZE U(32768) 34 # else 35 #define SOCFPGA_MMC_BLOCK_SIZE U(8192) 36 # endif 37 38 /* Register Mapping */ 39 #define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 40 #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) 41 42 #define SOCFPGA_MMC_REG_BASE 0xff808000 43 44 #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 45 #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 46 #define SOCFPGA_ECC_QSPI_REG_BASE 0xffa22000 47 48 #define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 49 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 50 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 51 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 52 53 /******************************************************************************* 54 * Platform memory map related constants 55 ******************************************************************************/ 56 #define DRAM_BASE (0x0) 57 #define DRAM_SIZE (0x80000000) 58 59 #define OCRAM_BASE (0xFFE00000) 60 #define OCRAM_SIZE (0x00040000) 61 62 #define MEM64_BASE (0x0100000000) 63 #define MEM64_SIZE (0x1F00000000) 64 65 #define DEVICE1_BASE (0x80000000) 66 #define DEVICE1_SIZE (0x60000000) 67 68 #define DEVICE2_BASE (0xF7000000) 69 #define DEVICE2_SIZE (0x08E00000) 70 71 #define DEVICE3_BASE (0xFFFC0000) 72 #define DEVICE3_SIZE (0x00008000) 73 74 #define DEVICE4_BASE (0x2000000000) 75 #define DEVICE4_SIZE (0x0100000000) 76 77 #define BL2_BASE (0xffe00000) 78 #define BL2_LIMIT (0xffe2b000) 79 80 #define BL31_BASE (0x1000) 81 #define BL31_LIMIT (0x81000) 82 83 /******************************************************************************* 84 * UART related constants 85 ******************************************************************************/ 86 #define PLAT_UART0_BASE (0xFFC02000) 87 #define PLAT_UART1_BASE (0xFFC02100) 88 89 /******************************************************************************* 90 * WDT related constants 91 ******************************************************************************/ 92 #define WDT_BASE (0xFFD00200) 93 94 /******************************************************************************* 95 * GIC related constants 96 ******************************************************************************/ 97 #define PLAT_GIC_BASE (0xFFFC0000) 98 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 99 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 100 #define PLAT_GICR_BASE 0 101 102 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) 103 #define PLAT_HZ_CONVERT_TO_MHZ (1000000) 104 105 /******************************************************************************* 106 * SDMMC related pointer function 107 ******************************************************************************/ 108 #define SDMMC_READ_BLOCKS mmc_read_blocks 109 #define SDMMC_WRITE_BLOCKS mmc_write_blocks 110 111 /******************************************************************************* 112 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 113 * is done and HPS should trigger warm reset via RMR_EL3. 114 ******************************************************************************/ 115 #define L2_RESET_DONE_REG 0xFFD12218 116 117 /* Platform specific system counter */ 118 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 119 120 #endif /* PLATSOCFPGA_DEF_H */ 121 122