1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <common/interrupt_props.h> 14 #include <common/tbbr/tbbr_img_def.h> 15 #include <plat/common/common_def.h> 16 #include "socfpga_plat_def.h" 17 18 /* Platform Type */ 19 #define PLAT_SOCFPGA_STRATIX10 1 20 #define PLAT_SOCFPGA_AGILEX 2 21 #define PLAT_SOCFPGA_N5X 3 22 #define PLAT_SOCFPGA_AGILEX5 4 23 #define SIMICS_RUN 1 24 #define MAX_IO_MTD_DEVICES U(1) 25 /* Boot Source configuration 26 * TODO: Shall consider "assert_numeric" in the future 27 */ 28 #if SOCFPGA_BOOT_SOURCE_NAND 29 #define BOOT_SOURCE BOOT_SOURCE_NAND 30 #elif SOCFPGA_BOOT_SOURCE_SDMMC 31 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 32 #elif SOCFPGA_BOOT_SOURCE_QSPI 33 #define BOOT_SOURCE BOOT_SOURCE_QSPI 34 #else 35 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 36 #endif 37 38 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ 39 #define PLAT_CPU_RELEASE_ADDR 0xffd12210 40 41 /* Magic word to indicate L2 reset is completed */ 42 #define L2_RESET_DONE_STATUS 0x1228E5E7 43 44 /* Define next boot image name and offset */ 45 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ 46 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 47 #ifndef PRELOADED_BL33_BASE 48 #define PLAT_NS_IMAGE_OFFSET 0x80200000 49 #else 50 #define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 51 #endif 52 #define PLAT_HANDOFF_OFFSET 0x0003F000 53 54 #else 55 /* Legacy Products. Please refactor with Agilex5 */ 56 #ifndef PRELOADED_BL33_BASE 57 #define PLAT_NS_IMAGE_OFFSET 0x10000000 58 #else 59 #define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 60 #endif 61 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 62 #endif 63 64 #define PLAT_QSPI_DATA_BASE (0x3C00000) 65 #define PLAT_NAND_DATA_BASE (0x0200000) 66 #define PLAT_SDMMC_DATA_BASE (0x0) 67 68 69 /******************************************************************************* 70 * Platform binary types for linking 71 ******************************************************************************/ 72 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 73 #define PLATFORM_LINKER_ARCH aarch64 74 75 /* SoCFPGA supports up to 124GB RAM */ 76 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 77 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 78 79 80 /******************************************************************************* 81 * Generic platform constants 82 ******************************************************************************/ 83 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 84 85 /* Size of cacheable stacks */ 86 #define PLATFORM_STACK_SIZE 0x2000 87 88 /* PSCI related constant */ 89 #define PLAT_NUM_POWER_DOMAINS 5 90 #define PLAT_MAX_PWR_LVL 1 91 #define PLAT_MAX_RET_STATE 1 92 #define PLAT_MAX_OFF_STATE 2 93 #define PLATFORM_SYSTEM_COUNT U(1) 94 #define PLATFORM_CLUSTER_COUNT U(1) 95 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 96 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 97 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 98 PLATFORM_CLUSTER0_CORE_COUNT) 99 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 100 101 /* Interrupt related constant */ 102 103 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 104 105 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 106 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 107 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 108 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 109 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 110 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 111 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 112 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 113 114 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 115 #define TSP_SEC_MEM_BASE BL32_BASE 116 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 117 118 119 /******************************************************************************* 120 * BL31 specific defines. 121 ******************************************************************************/ 122 /* 123 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 124 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 125 * little space for growth. 126 */ 127 128 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 129 130 #define BL1_RO_BASE (0xffe00000) 131 #define BL1_RO_LIMIT (0xffe0f000) 132 #define BL1_RW_BASE (0xffe10000) 133 #define BL1_RW_LIMIT (0xffe1ffff) 134 #define BL1_RW_SIZE (0x14000) 135 136 #define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET 137 138 #define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) 139 #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) 140 141 #define CMP_ENTRY 0xFFE3EFF8 142 143 #define PLAT_SEC_WARM_ENTRY 0 144 145 /******************************************************************************* 146 * Platform specific page table and MMU setup constants 147 ******************************************************************************/ 148 #define MAX_XLAT_TABLES 8 149 #define MAX_MMAP_REGIONS 16 150 151 /******************************************************************************* 152 * Declarations and constants to access the mailboxes safely. Each mailbox is 153 * aligned on the biggest cache line size in the platform. This is known only 154 * to the platform as it might have a combination of integrated and external 155 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 156 * line at any cache level. They could belong to different cpus/clusters & 157 * get written while being protected by different locks causing corruption of 158 * a valid mailbox address. 159 ******************************************************************************/ 160 #define CACHE_WRITEBACK_SHIFT 6 161 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 162 163 /******************************************************************************* 164 * UART related constants 165 ******************************************************************************/ 166 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 167 #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE 168 169 #define PLAT_BAUDRATE (115200) 170 #define PLAT_UART_CLOCK (100000000) 171 172 /******************************************************************************* 173 * PHY related constants 174 ******************************************************************************/ 175 176 #define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII 177 #define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII 178 #define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII 179 180 /******************************************************************************* 181 * GIC related constants 182 ******************************************************************************/ 183 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 184 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 185 186 /******************************************************************************* 187 * System counter frequency related constants 188 ******************************************************************************/ 189 190 /* 191 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 192 * terminology. On a GICv2 system or mode, the lists will be merged and treated 193 * as Group 0 interrupts. 194 */ 195 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 196 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 197 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 198 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 199 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 200 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 201 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 202 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 203 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 204 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 205 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 206 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 207 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 208 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 209 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 210 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 211 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 212 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 213 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 214 215 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 216 217 #define MAX_IO_HANDLES 4 218 #define MAX_IO_DEVICES 4 219 #define MAX_IO_BLOCK_DEVICES 2 220 221 #ifndef __ASSEMBLER__ 222 struct socfpga_bl31_params { 223 param_header_t h; 224 image_info_t *bl31_image_info; 225 entry_point_info_t *bl32_ep_info; 226 image_info_t *bl32_image_info; 227 entry_point_info_t *bl33_ep_info; 228 image_info_t *bl33_image_info; 229 }; 230 #endif 231 232 #endif /* PLATFORM_DEF_H */ 233