| 18e279eb | 12-Jun-2017 |
Soby Mathew <soby.mathew@arm.com> |
CSS: Changes for SDS framework
This patch does the required changes to enable CSS platforms
to build and use the SDS framework. Since SDS is always coupled with
SCMI protocol, the preexisting SCMI b
CSS: Changes for SDS framework
This patch does the required changes to enable CSS platforms
to build and use the SDS framework. Since SDS is always coupled with
SCMI protocol, the preexisting SCMI build flag is now renamed to
`CSS_USE_SCMI_SDS_DRIVER` which will enable both SCMI and SDS on
CSS platforms. Also some of the workarounds applied for SCMI are
now removed with SDS in place.
Change-Id: I94e8b93f05e3fe95e475c5501c25bec052588a9c
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| a87a1fb3 | 27-Aug-2017 |
Victor Chong <victor.chong@linaro.org> |
docs: hikey: Fix typo
Signed-off-by: Victor Chong <victor.chong@linaro.org> |
| a8eb286a | 31-Aug-2017 |
Soby Mathew <soby.mathew@arm.com> |
cert_tool: Support for legacy RSA PKCS#1 v1.5
This patch enables choice of RSA version at run time to be used for
generating signatures by the cert_tool. The RSA PSS as defined in
PKCS#1 v2.1 become
cert_tool: Support for legacy RSA PKCS#1 v1.5
This patch enables choice of RSA version at run time to be used for
generating signatures by the cert_tool. The RSA PSS as defined in
PKCS#1 v2.1 becomes the default version and this patch enables to specify
the RSA PKCS#1 v1.5 algorithm to `cert_create` through the command line
-a option. Also, the build option `KEY_ALG` can be used to pass this
option from the build system. Please note that RSA PSS is mandated
by Trusted Board Boot requirements (TBBR) and legacy RSA support is
being added for compatibility reasons.
Fixes ARM-Software/tf-issues#499
Change-Id: Ifaa3f2f7c9b43f3d7b3effe2cde76bf6745a5d73
Co-Authored-By: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| 2091755c | 31-Aug-2017 |
Soby Mathew <soby.mathew@arm.com> |
Export KEY_ALG as a user build option
The `KEY_ALG` variable is used to select the algorithm for key
generation by `cert_create` tool for signing the certificates. This
variable was previously undoc
Export KEY_ALG as a user build option
The `KEY_ALG` variable is used to select the algorithm for key
generation by `cert_create` tool for signing the certificates. This
variable was previously undocumented and did not have a global default
value. This patch corrects this and also adds changes to derive the
value of `TF_MBEDTLS_KEY_ALG` based on `KEY_ALG` if it not set by the
platform. The corresponding assignment of these variables are also now
removed from the `arm_common.mk` makefile.
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I78e2d6f4fc04ed5ad35ce2266118afb63127a5a4
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| b0c61f94 | 02-Aug-2017 |
Douglas Raillard <douglas.raillard@arm.com> |
porting-guide.rst: Fix some sections' level
Fix the level of the section
"13. Function : plat_setup_psci_ops() [mandatory]",
including all the subsections.
Fix the level of the section
"12.7. p
porting-guide.rst: Fix some sections' level
Fix the level of the section
"13. Function : plat_setup_psci_ops() [mandatory]",
including all the subsections.
Fix the level of the section
"12.7. plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]"
to lower it like the surrounding functions.
Change-Id: I781823bc96ece669f8fde4bd39c4e333c7bf4d1a
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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| bd359234 | 30-Aug-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1073 from davidcunado-arm/dc/update_docs
Add usage note for FVP model versions 11.0 and 8.5 |
| b15bab6b | 30-Aug-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1066 from islmit01/im/enable_cnp_bit
Enable CnP bit for ARMv8.2 CPUs |
| 279fedc1 | 31-Jul-2017 |
David Cunado <david.cunado@arm.com> |
Add usage note for FVP model versions 11.0 and 8.5
The internal synchronisation timings of the FVP model version
11.0 build 11.0.34 and version 8.5 build 0.8.5202 has been
changed compared to older
Add usage note for FVP model versions 11.0 and 8.5
The internal synchronisation timings of the FVP model version
11.0 build 11.0.34 and version 8.5 build 0.8.5202 has been
changed compared to older version of the models.
This change may have an impact on how the model behaves depending
on the workload being run on the model. For example test failures
have been seen where the primary core has powered on a secondary
core but was then starved of host CPU time and so was not able to
update power status, resulting a test failure due to an incorrect
status. This, or similar behaviour, is not to be expected from
real hardware platforms.
This patch adds a usage note on how to launch these models so
that internal synchronisation timing matches that of the older
version of the models, specifically adding the -Q 100 option.
Change-Id: If922afddba1581b7246ec889b3f1598533ea1b7e
Signed-off-by: David Cunado <david.cunado@arm.com>
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| 913c3842 | 29-Aug-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1056 from geesun/qx/interrupt-diags
update the interrupt diagrams |
| f91e8d1a | 25-Aug-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1067 from jeenu-arm/rst-fix
firmware-design.rst: Fix formatting |
| 9fce2725 | 07-Aug-2017 |
Isla Mitchell <isla.mitchell@arm.com> |
Enable CnP bit for ARMv8.2 CPUs
This patch enables the CnP (Common not Private) bit for secure page
tables so that multiple PEs in the same Inner Shareable domain can use
the same translation table
Enable CnP bit for ARMv8.2 CPUs
This patch enables the CnP (Common not Private) bit for secure page
tables so that multiple PEs in the same Inner Shareable domain can use
the same translation table entries for a given stage of translation in
a particular translation regime. This only takes effect when ARM
Trusted Firmware is built with ARM_ARCH_MINOR >= 2.
ARM Trusted Firmware Design has been updated to include a description
of this feature usage.
Change-Id: I698305f047400119aa1900d34c65368022e410b8
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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| 579b4adb | 24-Aug-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
firmware-design.rst: Fix formatting
The format conversion wrongly formatted a couple of sections. These were
also missing from the Table of Contents.
Change-Id: I324216c27e7b4711e6cc5e25782f4b53842
firmware-design.rst: Fix formatting
The format conversion wrongly formatted a couple of sections. These were
also missing from the Table of Contents.
Change-Id: I324216c27e7b4711e6cc5e25782f4b53842140cc
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| d591d766 | 23-Aug-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
doc: minor typo fix
Change-Id: I00fae047dea0eaf7e60037598af020817c66f659
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> |
| e8082422 | 17-Aug-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #977 from etienne-lms/sp-min-fiq
bl32: add secure interrupt handling in AArch32 sp_min |
| 7f943ba6 | 11-Jul-2017 |
Qixiang Xu <qixiang.xu@arm.com> |
update the interrupt diagrams
- Redraw the interrupt diagrams with dia tool
- Change TSP_HANDLED_S_EL1_FIQ to TSP_HANDLED_S_EL1_INTR in sec-int-handling.png
- Use the makefile generate the
update the interrupt diagrams
- Redraw the interrupt diagrams with dia tool
- Change TSP_HANDLED_S_EL1_FIQ to TSP_HANDLED_S_EL1_INTR in sec-int-handling.png
- Use the makefile generate the image to avoid unnessary generate
- Add dia source code
Change-Id: I016022ca964720e8497c27c88a3f371459abc284
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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| 1a52aca5 | 14-Aug-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1040 from sliai/support-opteed-header
Support opteed header |
| ebab9831 | 14-Aug-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1049 from sandrine-bailleux-arm/sb/xlat-lib-v2-doc
Add documentation of the xlat tables library V2 |
| a937d93e | 14-Aug-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1046 from jeenu-arm/revc
Support for RevC FVP model |
| 71816096 | 09-Aug-2017 |
Etienne Carriere <etienne.carriere@st.com> |
bl32: add secure interrupt handling in AArch32 sp_min
Add support for a minimal secure interrupt service in sp_min for
the AArch32 implementation. Hard code that only FIQs are handled.
Introduce bo
bl32: add secure interrupt handling in AArch32 sp_min
Add support for a minimal secure interrupt service in sp_min for
the AArch32 implementation. Hard code that only FIQs are handled.
Introduce bolean build directive SP_MIN_WITH_SECURE_FIQ to enable
FIQ handling from SP_MIN.
Configure SCR[FIQ] and SCR[FW] from generic code for both cold and
warm boots to handle FIQ in secure state from monitor.
Since SP_MIN architecture, FIQ are always trapped when system executes
in non secure state. Hence discard relay of the secure/non-secure
state in the FIQ handler.
Change-Id: I1f7d1dc7b21f6f90011b7f3fcd921e455592f5e7
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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| 71fb3964 | 20-Apr-2017 |
Summer Qin <summer.qin@arm.com> |
Support Trusted OS firmware extra images in TF tools
Since Trusted OS firmware may have extra images, need to
assign new uuid and image id for them.
The TBBR chain of trust has been extended to add
Support Trusted OS firmware extra images in TF tools
Since Trusted OS firmware may have extra images, need to
assign new uuid and image id for them.
The TBBR chain of trust has been extended to add support
for the new images within the existing Trusted OS firmware
content certificate.
Change-Id: I678dac7ba1137e85c5779b05e0c4331134c10e06
Signed-off-by: Summer Qin <summer.qin@arm.com>
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| 6feb9e88 | 23-May-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Add documentation of the xlat tables library V2
The documentation describes the design of the translation tables
library version 2 used by the ARM Trusted Firmware.
The diagram file has been create
Add documentation of the xlat tables library V2
The documentation describes the design of the translation tables
library version 2 used by the ARM Trusted Firmware.
The diagram file has been created with Dia version 0.97.2. This tool
can be obtained from: https://wiki.gnome.org/Apps/Dia/Download
Inkscape has been used to generate the *.png file from the *.dia file
to work around a bug in the generation of *.png files in some versions
of Dia.
Change-Id: Ie67d9998d4ae881b2c060200a318ad3ac2fa5e91
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 1a3a1676 | 19-Jul-2017 |
David Cunado <david.cunado@arm.com> |
Fix to change.log
With the migration to .rst from .md, the Issues Resolved and
Known Issues sections for v1.4 were using Header 1 format.
This patch changes to using Header 2 for these sections.
C
Fix to change.log
With the migration to .rst from .md, the Issues Resolved and
Known Issues sections for v1.4 were using Header 1 format.
This patch changes to using Header 2 for these sections.
Change-Id: Ic3127d84eb169a65039fd4cc8284c6429302732d
Signed-off-by: David Cunado <david.cunado@arm.com>
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| e33fd445 | 19-Jul-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
CCI: Adapt for specific product at run time
The current build system and driver requires the CCI product to be
specified at build time. The device constraints can be determined at run
time from its
CCI: Adapt for specific product at run time
The current build system and driver requires the CCI product to be
specified at build time. The device constraints can be determined at run
time from its ID registers, obviating the need for specifying them
ahead.
This patch adds changes to identify and validate CCI at run time. Some
global variables are renamed to be in line with the rest of the code
base.
The build option ARM_CCI_PRODUCT_ID is now removed, and user guide is
updated.
Change-Id: Ibb765e349d3bc95ff3eb9a64bde1207ab710a93d
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 11ad8f20 | 15-Nov-2016 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
FVP: Add support for multi-threaded CPUs
ARM CPUs with multi-threading implementation has more than one
Processing Element in a single physical CPU. Such an implementation will
reflect the following
FVP: Add support for multi-threaded CPUs
ARM CPUs with multi-threading implementation has more than one
Processing Element in a single physical CPU. Such an implementation will
reflect the following changes in the MPIDR register:
- The MT bit set;
- Affinity levels pertaining to cluster and CPUs occupy one level
higher than in a single-threaded implementation, and the lowest
affinity level pertains to hardware threads. MPIDR affinity level
fields essentially appear shifted to left than otherwise.
The FVP port henceforth assumes that both properties above to be
concomitant on a given FVP platform.
To accommodate for varied MPIDR formats at run time, this patch
re-implements the FVP platform-specific functions that translates MPIDR
values to a linear indices, along with required validation. The same
treatment is applied for GICv3 MPIDR hashing function as well.
An FVP-specific build option FVP_MAX_PE_PER_CPU is introduced which
specifies the maximum number of threads implemented per CPU. For
backwards compatibility, its value defaults to 1.
Change-Id: I729b00d3e121d16ce9a03de4f9db36dfac580e3f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 1862d620 | 10-Jul-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
lib: psci: early suspend handler for platforms
This patch adds an early suspend handler, that executes with
SMP and data cache enabled. This handler allows platforms to
perform any early actions dur
lib: psci: early suspend handler for platforms
This patch adds an early suspend handler, that executes with
SMP and data cache enabled. This handler allows platforms to
perform any early actions during the CPU suspend entry sequence.
This handler is optional and platforms can choose to implement it
depending on their needs. The `pwr_domain_suspend` handler still
exists and platforms can keep on using it without any side effects.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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