1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <debug.h> 36 #include <errno.h> 37 #include <memctrl.h> 38 #include <runtime_svc.h> 39 #include <tegra_private.h> 40 #include <tegra_platform.h> 41 42 /******************************************************************************* 43 * Common Tegra SiP SMCs 44 ******************************************************************************/ 45 #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 46 #define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005 47 #define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006 48 #define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2000007 49 50 /******************************************************************************* 51 * Fake system suspend mode control var 52 ******************************************************************************/ 53 extern uint8_t tegra_fake_system_suspend; 54 55 56 /******************************************************************************* 57 * SoC specific SiP handler 58 ******************************************************************************/ 59 #pragma weak plat_sip_handler 60 int plat_sip_handler(uint32_t smc_fid, 61 uint64_t x1, 62 uint64_t x2, 63 uint64_t x3, 64 uint64_t x4, 65 void *cookie, 66 void *handle, 67 uint64_t flags) 68 { 69 return -ENOTSUP; 70 } 71 72 /******************************************************************************* 73 * This function is responsible for handling all SiP calls 74 ******************************************************************************/ 75 uint64_t tegra_sip_handler(uint32_t smc_fid, 76 uint64_t x1, 77 uint64_t x2, 78 uint64_t x3, 79 uint64_t x4, 80 void *cookie, 81 void *handle, 82 uint64_t flags) 83 { 84 int err; 85 86 /* Check if this is a SoC specific SiP */ 87 err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 88 if (err == 0) 89 SMC_RET1(handle, (uint64_t)err); 90 91 switch (smc_fid) { 92 93 case TEGRA_SIP_NEW_VIDEOMEM_REGION: 94 95 /* clean up the high bits */ 96 x2 = (uint32_t)x2; 97 98 /* 99 * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) 100 * or falls outside of the valid DRAM range 101 */ 102 err = bl31_check_ns_address(x1, x2); 103 if (err) 104 SMC_RET1(handle, err); 105 106 /* 107 * Check if Video Memory is aligned to 1MB. 108 */ 109 if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { 110 ERROR("Unaligned Video Memory base address!\n"); 111 SMC_RET1(handle, -ENOTSUP); 112 } 113 114 /* new video memory carveout settings */ 115 tegra_memctrl_videomem_setup(x1, x2); 116 117 SMC_RET1(handle, 0); 118 break; 119 120 /* 121 * The NS world registers the address of its handler to be 122 * used for processing the FIQ. This is normally used by the 123 * NS FIQ debugger driver to detect system hangs by programming 124 * a watchdog timer to fire a FIQ interrupt. 125 */ 126 case TEGRA_SIP_FIQ_NS_ENTRYPOINT: 127 128 if (!x1) 129 SMC_RET1(handle, SMC_UNK); 130 131 /* 132 * TODO: Check if x1 contains a valid DRAM address 133 */ 134 135 /* store the NS world's entrypoint */ 136 tegra_fiq_set_ns_entrypoint(x1); 137 138 SMC_RET1(handle, 0); 139 break; 140 141 /* 142 * The NS world's FIQ handler issues this SMC to get the NS EL1/EL0 143 * CPU context when the FIQ interrupt was triggered. This allows the 144 * NS world to understand the CPU state when the watchdog interrupt 145 * triggered. 146 */ 147 case TEGRA_SIP_FIQ_NS_GET_CONTEXT: 148 149 /* retrieve context registers when FIQ triggered */ 150 tegra_fiq_get_intr_context(); 151 152 SMC_RET0(handle); 153 break; 154 155 case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND: 156 /* 157 * System suspend fake mode is set if we are on VDK and we make 158 * a debug SIP call. This mode ensures that we excercise debug 159 * path instead of the regular code path to suit the pre-silicon 160 * platform needs. These include replacing the call to WFI by 161 * a warm reset request. 162 */ 163 if (tegra_platform_is_emulation() != 0U) { 164 165 tegra_fake_system_suspend = 1; 166 SMC_RET1(handle, 0); 167 } 168 169 /* 170 * We return to the external world as if this SIP is not 171 * implemented in case, we are not running on VDK. 172 */ 173 break; 174 175 default: 176 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 177 break; 178 } 179 180 SMC_RET1(handle, SMC_UNK); 181 } 182 183 /* Define a runtime service descriptor for fast SMC calls */ 184 DECLARE_RT_SVC( 185 tegra_sip_fast, 186 187 OEN_SIP_START, 188 OEN_SIP_END, 189 SMC_TYPE_FAST, 190 NULL, 191 tegra_sip_handler 192 ); 193