1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <assert_macros.S> 33#include <cortex_a57.h> 34#include <cpu_macros.S> 35#include <debug.h> 36 37 /* --------------------------------------------- 38 * Disable intra-cluster coherency 39 * Clobbers: r0-r1 40 * --------------------------------------------- 41 */ 42func cortex_a57_disable_smp 43 ldcopr16 r0, r1, CPUECTLR 44 bic64_imm r0, r1, CPUECTLR_SMP_BIT 45 stcopr16 r0, r1, CPUECTLR 46 bx lr 47endfunc cortex_a57_disable_smp 48 49 /* --------------------------------------------- 50 * Disable all types of L2 prefetches. 51 * Clobbers: r0-r2 52 * --------------------------------------------- 53 */ 54func cortex_a57_disable_l2_prefetch 55 ldcopr16 r0, r1, CPUECTLR 56 orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT 57 bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \ 58 CPUECTLR_L2_DPFTCH_DIST_MASK) 59 stcopr16 r0, r1, CPUECTLR 60 isb 61 dsb ish 62 bx lr 63endfunc cortex_a57_disable_l2_prefetch 64 65 /* --------------------------------------------- 66 * Disable debug interfaces 67 * --------------------------------------------- 68 */ 69func cortex_a57_disable_ext_debug 70 mov r0, #1 71 stcopr r0, DBGOSDLR 72 isb 73 dsb sy 74 bx lr 75endfunc cortex_a57_disable_ext_debug 76 77 /* ------------------------------------------------- 78 * The CPU Ops reset function for Cortex-A57. 79 * ------------------------------------------------- 80 */ 81func cortex_a57_reset_func 82 /* --------------------------------------------- 83 * Enable the SMP bit. 84 * --------------------------------------------- 85 */ 86 ldcopr16 r0, r1, CPUECTLR 87 orr64_imm r0, r1, CPUECTLR_SMP_BIT 88 stcopr16 r0, r1, CPUECTLR 89 isb 90 bx lr 91endfunc cortex_a57_reset_func 92 93 /* ---------------------------------------------------- 94 * The CPU Ops core power down function for Cortex-A57. 95 * ---------------------------------------------------- 96 */ 97func cortex_a57_core_pwr_dwn 98 push {r12, lr} 99 100 /* Assert if cache is enabled */ 101#if ASM_ASSERTION 102 ldcopr r0, SCTLR 103 tst r0, #SCTLR_C_BIT 104 ASM_ASSERT(eq) 105#endif 106 107 /* --------------------------------------------- 108 * Disable the L2 prefetches. 109 * --------------------------------------------- 110 */ 111 bl cortex_a57_disable_l2_prefetch 112 113 /* --------------------------------------------- 114 * Flush L1 caches. 115 * --------------------------------------------- 116 */ 117 mov r0, #DC_OP_CISW 118 bl dcsw_op_level1 119 120 /* --------------------------------------------- 121 * Come out of intra cluster coherency 122 * --------------------------------------------- 123 */ 124 bl cortex_a57_disable_smp 125 126 /* --------------------------------------------- 127 * Force the debug interfaces to be quiescent 128 * --------------------------------------------- 129 */ 130 pop {r12, lr} 131 b cortex_a57_disable_ext_debug 132endfunc cortex_a57_core_pwr_dwn 133 134 /* ------------------------------------------------------- 135 * The CPU Ops cluster power down function for Cortex-A57. 136 * Clobbers: r0-r3 137 * ------------------------------------------------------- 138 */ 139func cortex_a57_cluster_pwr_dwn 140 push {r12, lr} 141 142 /* Assert if cache is enabled */ 143#if ASM_ASSERTION 144 ldcopr r0, SCTLR 145 tst r0, #SCTLR_C_BIT 146 ASM_ASSERT(eq) 147#endif 148 149 /* --------------------------------------------- 150 * Disable the L2 prefetches. 151 * --------------------------------------------- 152 */ 153 bl cortex_a57_disable_l2_prefetch 154 155 /* --------------------------------------------- 156 * Flush L1 caches. 157 * --------------------------------------------- 158 */ 159 mov r0, #DC_OP_CISW 160 bl dcsw_op_level1 161 162 /* --------------------------------------------- 163 * Disable the optional ACP. 164 * --------------------------------------------- 165 */ 166 bl plat_disable_acp 167 168 /* --------------------------------------------- 169 * Flush L2 caches. 170 * --------------------------------------------- 171 */ 172 mov r0, #DC_OP_CISW 173 bl dcsw_op_level2 174 175 /* --------------------------------------------- 176 * Come out of intra cluster coherency 177 * --------------------------------------------- 178 */ 179 bl cortex_a57_disable_smp 180 181 /* --------------------------------------------- 182 * Force the debug interfaces to be quiescent 183 * --------------------------------------------- 184 */ 185 pop {r12, lr} 186 b cortex_a57_disable_ext_debug 187endfunc cortex_a57_cluster_pwr_dwn 188 189declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ 190 cortex_a57_reset_func, \ 191 cortex_a57_core_pwr_dwn, \ 192 cortex_a57_cluster_pwr_dwn 193