1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arm_def.h> 33 #include <arm_xlat_tables.h> 34 #include <bl_common.h> 35 #include <console.h> 36 #include <platform_def.h> 37 #include <plat_arm.h> 38 #include <sp805.h> 39 #include <utils.h> 40 #include "../../../bl1/bl1_private.h" 41 42 /* Weak definitions may be overridden in specific ARM standard platform */ 43 #pragma weak bl1_early_platform_setup 44 #pragma weak bl1_plat_arch_setup 45 #pragma weak bl1_platform_setup 46 #pragma weak bl1_plat_sec_mem_layout 47 #pragma weak bl1_plat_prepare_exit 48 49 50 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 51 static meminfo_t bl1_tzram_layout; 52 53 meminfo_t *bl1_plat_sec_mem_layout(void) 54 { 55 return &bl1_tzram_layout; 56 } 57 58 /******************************************************************************* 59 * BL1 specific platform actions shared between ARM standard platforms. 60 ******************************************************************************/ 61 void arm_bl1_early_platform_setup(void) 62 { 63 64 #if !ARM_DISABLE_TRUSTED_WDOG 65 /* Enable watchdog */ 66 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 67 #endif 68 69 /* Initialize the console to provide early debug support */ 70 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 71 ARM_CONSOLE_BAUDRATE); 72 73 /* Allow BL1 to see the whole Trusted RAM */ 74 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 75 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 76 77 #if !LOAD_IMAGE_V2 78 /* Calculate how much RAM BL1 is using and how much remains free */ 79 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE; 80 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE; 81 reserve_mem(&bl1_tzram_layout.free_base, 82 &bl1_tzram_layout.free_size, 83 BL1_RAM_BASE, 84 BL1_RAM_LIMIT - BL1_RAM_BASE); 85 #endif /* LOAD_IMAGE_V2 */ 86 } 87 88 void bl1_early_platform_setup(void) 89 { 90 arm_bl1_early_platform_setup(); 91 92 /* 93 * Initialize Interconnect for this cluster during cold boot. 94 * No need for locks as no other CPU is active. 95 */ 96 plat_arm_interconnect_init(); 97 /* 98 * Enable Interconnect coherency for the primary CPU's cluster. 99 */ 100 plat_arm_interconnect_enter_coherency(); 101 } 102 103 /****************************************************************************** 104 * Perform the very early platform specific architecture setup shared between 105 * ARM standard platforms. This only does basic initialization. Later 106 * architectural setup (bl1_arch_setup()) does not do anything platform 107 * specific. 108 *****************************************************************************/ 109 void arm_bl1_plat_arch_setup(void) 110 { 111 arm_setup_page_tables(bl1_tzram_layout.total_base, 112 bl1_tzram_layout.total_size, 113 BL_CODE_BASE, 114 BL1_CODE_END, 115 BL1_RO_DATA_BASE, 116 BL1_RO_DATA_END 117 #if USE_COHERENT_MEM 118 , BL_COHERENT_RAM_BASE, 119 BL_COHERENT_RAM_END 120 #endif 121 ); 122 #ifdef AARCH32 123 enable_mmu_secure(0); 124 #else 125 enable_mmu_el3(0); 126 #endif /* AARCH32 */ 127 } 128 129 void bl1_plat_arch_setup(void) 130 { 131 arm_bl1_plat_arch_setup(); 132 } 133 134 /* 135 * Perform the platform specific architecture setup shared between 136 * ARM standard platforms. 137 */ 138 void arm_bl1_platform_setup(void) 139 { 140 /* Initialise the IO layer and register platform IO devices */ 141 plat_arm_io_setup(); 142 } 143 144 void bl1_platform_setup(void) 145 { 146 arm_bl1_platform_setup(); 147 } 148 149 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 150 { 151 #if !ARM_DISABLE_TRUSTED_WDOG 152 /* Disable watchdog before leaving BL1 */ 153 sp805_stop(ARM_SP805_TWDG_BASE); 154 #endif 155 156 #ifdef EL3_PAYLOAD_BASE 157 /* 158 * Program the EL3 payload's entry point address into the CPUs mailbox 159 * in order to release secondary CPUs from their holding pen and make 160 * them jump there. 161 */ 162 arm_program_trusted_mailbox(ep_info->pc); 163 dsbsy(); 164 sev(); 165 #endif 166 } 167