1/* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <platform_def.h> 32 33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 34OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 35ENTRY(bl31_entrypoint) 36 37 38MEMORY { 39 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE 40} 41 42#ifdef PLAT_EXTRA_LD_SCRIPT 43#include <plat.ld.S> 44#endif 45 46SECTIONS 47{ 48 . = BL31_BASE; 49 ASSERT(. == ALIGN(4096), 50 "BL31_BASE address is not aligned on a page boundary.") 51 52#if SEPARATE_CODE_AND_RODATA 53 .text . : { 54 __TEXT_START__ = .; 55 *bl31_entrypoint.o(.text*) 56 *(.text*) 57 *(.vectors) 58 . = NEXT(4096); 59 __TEXT_END__ = .; 60 } >RAM 61 62 .rodata . : { 63 __RODATA_START__ = .; 64 *(.rodata*) 65 66 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 67 . = ALIGN(8); 68 __RT_SVC_DESCS_START__ = .; 69 KEEP(*(rt_svc_descs)) 70 __RT_SVC_DESCS_END__ = .; 71 72#if ENABLE_PMF 73 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 74 . = ALIGN(8); 75 __PMF_SVC_DESCS_START__ = .; 76 KEEP(*(pmf_svc_descs)) 77 __PMF_SVC_DESCS_END__ = .; 78#endif /* ENABLE_PMF */ 79 80 /* 81 * Ensure 8-byte alignment for cpu_ops so that its fields are also 82 * aligned. Also ensure cpu_ops inclusion. 83 */ 84 . = ALIGN(8); 85 __CPU_OPS_START__ = .; 86 KEEP(*(cpu_ops)) 87 __CPU_OPS_END__ = .; 88 89 . = NEXT(4096); 90 __RODATA_END__ = .; 91 } >RAM 92#else 93 ro . : { 94 __RO_START__ = .; 95 *bl31_entrypoint.o(.text*) 96 *(.text*) 97 *(.rodata*) 98 99 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 100 . = ALIGN(8); 101 __RT_SVC_DESCS_START__ = .; 102 KEEP(*(rt_svc_descs)) 103 __RT_SVC_DESCS_END__ = .; 104 105#if ENABLE_PMF 106 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 107 . = ALIGN(8); 108 __PMF_SVC_DESCS_START__ = .; 109 KEEP(*(pmf_svc_descs)) 110 __PMF_SVC_DESCS_END__ = .; 111#endif /* ENABLE_PMF */ 112 113 /* 114 * Ensure 8-byte alignment for cpu_ops so that its fields are also 115 * aligned. Also ensure cpu_ops inclusion. 116 */ 117 . = ALIGN(8); 118 __CPU_OPS_START__ = .; 119 KEEP(*(cpu_ops)) 120 __CPU_OPS_END__ = .; 121 122 *(.vectors) 123 __RO_END_UNALIGNED__ = .; 124 /* 125 * Memory page(s) mapped to this section will be marked as read-only, 126 * executable. No RW data from the next section must creep in. 127 * Ensure the rest of the current memory page is unused. 128 */ 129 . = NEXT(4096); 130 __RO_END__ = .; 131 } >RAM 132#endif 133 134 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 135 "cpu_ops not defined for this platform.") 136 137 /* 138 * Define a linker symbol to mark start of the RW memory area for this 139 * image. 140 */ 141 __RW_START__ = . ; 142 143 /* 144 * .data must be placed at a lower address than the stacks if the stack 145 * protector is enabled. Alternatively, the .data.stack_protector_canary 146 * section can be placed independently of the main .data section. 147 */ 148 .data . : { 149 __DATA_START__ = .; 150 *(.data*) 151 __DATA_END__ = .; 152 } >RAM 153 154#ifdef BL31_PROGBITS_LIMIT 155 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") 156#endif 157 158 stacks (NOLOAD) : { 159 __STACKS_START__ = .; 160 *(tzfw_normal_stacks) 161 __STACKS_END__ = .; 162 } >RAM 163 164 /* 165 * The .bss section gets initialised to 0 at runtime. 166 * Its base address should be 16-byte aligned for better performance of the 167 * zero-initialization code. 168 */ 169 .bss (NOLOAD) : ALIGN(16) { 170 __BSS_START__ = .; 171 *(.bss*) 172 *(COMMON) 173#if !USE_COHERENT_MEM 174 /* 175 * Bakery locks are stored in normal .bss memory 176 * 177 * Each lock's data is spread across multiple cache lines, one per CPU, 178 * but multiple locks can share the same cache line. 179 * The compiler will allocate enough memory for one CPU's bakery locks, 180 * the remaining cache lines are allocated by the linker script 181 */ 182 . = ALIGN(CACHE_WRITEBACK_GRANULE); 183 __BAKERY_LOCK_START__ = .; 184 *(bakery_lock) 185 . = ALIGN(CACHE_WRITEBACK_GRANULE); 186 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); 187 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 188 __BAKERY_LOCK_END__ = .; 189#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 190 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 191 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 192#endif 193#endif 194 195#if ENABLE_PMF 196 /* 197 * Time-stamps are stored in normal .bss memory 198 * 199 * The compiler will allocate enough memory for one CPU's time-stamps, 200 * the remaining memory for other CPU's is allocated by the 201 * linker script 202 */ 203 . = ALIGN(CACHE_WRITEBACK_GRANULE); 204 __PMF_TIMESTAMP_START__ = .; 205 KEEP(*(pmf_timestamp_array)) 206 . = ALIGN(CACHE_WRITEBACK_GRANULE); 207 __PMF_PERCPU_TIMESTAMP_END__ = .; 208 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 209 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 210 __PMF_TIMESTAMP_END__ = .; 211#endif /* ENABLE_PMF */ 212 __BSS_END__ = .; 213 } >RAM 214 215 /* 216 * The xlat_table section is for full, aligned page tables (4K). 217 * Removing them from .bss avoids forcing 4K alignment on 218 * the .bss section and eliminates the unecessary zero init 219 */ 220 xlat_table (NOLOAD) : { 221 *(xlat_table) 222 } >RAM 223 224#if USE_COHERENT_MEM 225 /* 226 * The base address of the coherent memory section must be page-aligned (4K) 227 * to guarantee that the coherent data are stored on their own pages and 228 * are not mixed with normal data. This is required to set up the correct 229 * memory attributes for the coherent data page tables. 230 */ 231 coherent_ram (NOLOAD) : ALIGN(4096) { 232 __COHERENT_RAM_START__ = .; 233 /* 234 * Bakery locks are stored in coherent memory 235 * 236 * Each lock's data is contiguous and fully allocated by the compiler 237 */ 238 *(bakery_lock) 239 *(tzfw_coherent_mem) 240 __COHERENT_RAM_END_UNALIGNED__ = .; 241 /* 242 * Memory page(s) mapped to this section will be marked 243 * as device memory. No other unexpected data must creep in. 244 * Ensure the rest of the current memory page is unused. 245 */ 246 . = NEXT(4096); 247 __COHERENT_RAM_END__ = .; 248 } >RAM 249#endif 250 251 /* 252 * Define a linker symbol to mark end of the RW memory area for this 253 * image. 254 */ 255 __RW_END__ = .; 256 __BL31_END__ = .; 257 258 __BSS_SIZE__ = SIZEOF(.bss); 259#if USE_COHERENT_MEM 260 __COHERENT_RAM_UNALIGNED_SIZE__ = 261 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 262#endif 263 264 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") 265} 266