1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __XLAT_TABLES_DEFS_H__ 8 #define __XLAT_TABLES_DEFS_H__ 9 10 #include <utils_def.h> 11 12 /* Miscellaneous MMU related constants */ 13 #define NUM_2MB_IN_GB (1 << 9) 14 #define NUM_4K_IN_2MB (1 << 9) 15 #define NUM_GB_IN_4GB (1 << 2) 16 17 #define TWO_MB_SHIFT 21 18 #define ONE_GB_SHIFT 30 19 #define FOUR_KB_SHIFT 12 20 21 #define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) 22 #define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) 23 #define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) 24 25 #define INVALID_DESC 0x0 26 #define BLOCK_DESC 0x1 /* Table levels 0-2 */ 27 #define TABLE_DESC 0x3 /* Table levels 0-2 */ 28 #define PAGE_DESC 0x3 /* Table level 3 */ 29 #define DESC_MASK 0x3 30 31 #define FIRST_LEVEL_DESC_N ONE_GB_SHIFT 32 #define SECOND_LEVEL_DESC_N TWO_MB_SHIFT 33 #define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT 34 35 /* XN: Translation regimes that support one VA range (EL2 and EL3). */ 36 #define XN (ULL(1) << 2) 37 /* UXN, PXN: Translation regimes that support two VA ranges (EL1&0). */ 38 #define UXN (ULL(1) << 2) 39 #define PXN (ULL(1) << 1) 40 #define CONT_HINT (ULL(1) << 0) 41 #define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52) 42 43 #define NON_GLOBAL (1 << 9) 44 #define ACCESS_FLAG (1 << 8) 45 #define NSH (0x0 << 6) 46 #define OSH (0x2 << 6) 47 #define ISH (0x3 << 6) 48 49 #define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000) 50 51 #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT /* 4, 16 or 64 KB */ 52 #define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) 53 #define PAGE_SIZE_MASK (PAGE_SIZE - 1) 54 #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) 55 56 #define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */ 57 #define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT) 58 59 #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ 60 #define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT) 61 62 #ifdef AARCH32 63 #define XLAT_TABLE_LEVEL_MIN 1 64 #else 65 #define XLAT_TABLE_LEVEL_MIN 0 66 #endif /* AARCH32 */ 67 68 #define XLAT_TABLE_LEVEL_MAX 3 69 70 /* Values for number of entries in each MMU translation table */ 71 #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) 72 #define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT) 73 #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) 74 75 /* Values to convert a memory address to an index into a translation table */ 76 #define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT 77 #define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 78 #define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 79 #define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 80 #define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \ 81 ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT)) 82 83 #define XLAT_BLOCK_SIZE(level) ((u_register_t)1 << XLAT_ADDR_SHIFT(level)) 84 /* Mask to get the bits used to index inside a block of a certain level */ 85 #define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - 1) 86 /* Mask to get the address bits common to a block of a certain table level*/ 87 #define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level)) 88 89 /* 90 * AP[1] bit is ignored by hardware and is 91 * treated as if it is One in EL2/EL3 92 */ 93 #define AP_RO (0x1 << 5) 94 #define AP_RW (0x0 << 5) 95 96 #define NS (0x1 << 3) 97 #define ATTR_NON_CACHEABLE_INDEX 0x2 98 #define ATTR_DEVICE_INDEX 0x1 99 #define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 100 #define LOWER_ATTRS(x) (((x) & 0xfff) << 2) 101 /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */ 102 #define ATTR_NON_CACHEABLE (0x44) 103 /* Device-nGnRE */ 104 #define ATTR_DEVICE (0x4) 105 /* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */ 106 #define ATTR_IWBWA_OWBWA_NTR (0xff) 107 #define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3)) 108 #define ATTR_INDEX_MASK 0x3 109 #define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK) 110 111 /* 112 * Flags to override default values used to program system registers while 113 * enabling the MMU. 114 */ 115 #define DISABLE_DCACHE (1 << 0) 116 117 /* 118 * This flag marks the translation tables are Non-cacheable for MMU accesses. 119 * If the flag is not specified, by default the tables are cacheable. 120 */ 121 #define XLAT_TABLE_NC (1 << 1) 122 123 #endif /* __XLAT_TABLES_DEFS_H__ */ 124