xref: /rk3399_ARM-atf/plat/arm/board/juno/juno_bl2_setup.c (revision b10d44995eb652675863c2cc6a7726683613da0d)
1 /*
2  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * Redistributions of source code must retain the above copyright notice, this
8  * list of conditions and the following disclaimer.
9  *
10  * Redistributions in binary form must reproduce the above copyright notice,
11  * this list of conditions and the following disclaimer in the documentation
12  * and/or other materials provided with the distribution.
13  *
14  * Neither the name of ARM nor the names of its contributors may be used
15  * to endorse or promote products derived from this software without specific
16  * prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  * POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 #include <assert.h>
32 #include <bl_common.h>
33 #include <desc_image_load.h>
34 #include <plat_arm.h>
35 
36 #if JUNO_AARCH32_EL3_RUNTIME
37 /*******************************************************************************
38  * This function changes the spsr for BL32 image to bypass
39  * the check in BL1 AArch64 exception handler. This is needed in the aarch32
40  * boot flow as the core comes up in aarch64 and to enter the BL32 image a warm
41  * reset in aarch32 state is required.
42  ******************************************************************************/
43 int bl2_plat_handle_post_image_load(unsigned int image_id)
44 {
45 	int err = arm_bl2_handle_post_image_load(image_id);
46 
47 	if (!err && (image_id == BL32_IMAGE_ID)) {
48 		bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
49 		assert(bl_mem_params);
50 		bl_mem_params->ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
51 			DISABLE_ALL_EXCEPTIONS);
52 	}
53 
54 	return err;
55 }
56 #endif /* JUNO_AARCH32_EL3_RUNTIME */
57