1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <assert_macros.S> 33#include <cortex_a72.h> 34#include <cpu_macros.S> 35#include <debug.h> 36 37 /* --------------------------------------------- 38 * Disable all types of L2 prefetches. 39 * --------------------------------------------- 40 */ 41func cortex_a72_disable_l2_prefetch 42 ldcopr16 r0, r1, CPUECTLR 43 orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT 44 bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \ 45 CPUECTLR_L2_DPFTCH_DIST_MASK) 46 stcopr16 r0, r1, CPUECTLR 47 isb 48 bx lr 49endfunc cortex_a72_disable_l2_prefetch 50 51 /* --------------------------------------------- 52 * Disable the load-store hardware prefetcher. 53 * --------------------------------------------- 54 */ 55func cortex_a72_disable_hw_prefetcher 56 ldcopr16 r0, r1, CPUACTLR 57 orr64_imm r0, r1, CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH 58 stcopr16 r0, r1, CPUACTLR 59 isb 60 dsb ish 61 bx lr 62endfunc cortex_a72_disable_hw_prefetcher 63 64 /* --------------------------------------------- 65 * Disable intra-cluster coherency 66 * Clobbers: r0-r1 67 * --------------------------------------------- 68 */ 69func cortex_a72_disable_smp 70 ldcopr16 r0, r1, CPUECTLR 71 bic64_imm r0, r1, CPUECTLR_SMP_BIT 72 stcopr16 r0, r1, CPUECTLR 73 bx lr 74endfunc cortex_a72_disable_smp 75 76 /* --------------------------------------------- 77 * Disable debug interfaces 78 * --------------------------------------------- 79 */ 80func cortex_a72_disable_ext_debug 81 mov r0, #1 82 stcopr r0, DBGOSDLR 83 isb 84 dsb sy 85 bx lr 86endfunc cortex_a72_disable_ext_debug 87 88 /* ------------------------------------------------- 89 * The CPU Ops reset function for Cortex-A72. 90 * ------------------------------------------------- 91 */ 92func cortex_a72_reset_func 93 /* --------------------------------------------- 94 * Enable the SMP bit. 95 * --------------------------------------------- 96 */ 97 ldcopr16 r0, r1, CPUECTLR 98 orr64_imm r0, r1, CPUECTLR_SMP_BIT 99 stcopr16 r0, r1, CPUECTLR 100 isb 101 bx lr 102endfunc cortex_a72_reset_func 103 104 /* ---------------------------------------------------- 105 * The CPU Ops core power down function for Cortex-A72. 106 * ---------------------------------------------------- 107 */ 108func cortex_a72_core_pwr_dwn 109 push {r12, lr} 110 111 /* Assert if cache is enabled */ 112#if ASM_ASSERTION 113 ldcopr r0, SCTLR 114 tst r0, #SCTLR_C_BIT 115 ASM_ASSERT(eq) 116#endif 117 118 /* --------------------------------------------- 119 * Disable the L2 prefetches. 120 * --------------------------------------------- 121 */ 122 bl cortex_a72_disable_l2_prefetch 123 124 /* --------------------------------------------- 125 * Disable the load-store hardware prefetcher. 126 * --------------------------------------------- 127 */ 128 bl cortex_a72_disable_hw_prefetcher 129 130 /* --------------------------------------------- 131 * Flush L1 caches. 132 * --------------------------------------------- 133 */ 134 mov r0, #DC_OP_CISW 135 bl dcsw_op_level1 136 137 /* --------------------------------------------- 138 * Come out of intra cluster coherency 139 * --------------------------------------------- 140 */ 141 bl cortex_a72_disable_smp 142 143 /* --------------------------------------------- 144 * Force the debug interfaces to be quiescent 145 * --------------------------------------------- 146 */ 147 pop {r12, lr} 148 b cortex_a72_disable_ext_debug 149endfunc cortex_a72_core_pwr_dwn 150 151 /* ------------------------------------------------------- 152 * The CPU Ops cluster power down function for Cortex-A72. 153 * ------------------------------------------------------- 154 */ 155func cortex_a72_cluster_pwr_dwn 156 push {r12, lr} 157 158 /* Assert if cache is enabled */ 159#if ASM_ASSERTION 160 ldcopr r0, SCTLR 161 tst r0, #SCTLR_C_BIT 162 ASM_ASSERT(eq) 163#endif 164 165 /* --------------------------------------------- 166 * Disable the L2 prefetches. 167 * --------------------------------------------- 168 */ 169 bl cortex_a72_disable_l2_prefetch 170 171 /* --------------------------------------------- 172 * Disable the load-store hardware prefetcher. 173 * --------------------------------------------- 174 */ 175 bl cortex_a72_disable_hw_prefetcher 176 177#if !SKIP_A72_L1_FLUSH_PWR_DWN 178 /* --------------------------------------------- 179 * Flush L1 caches. 180 * --------------------------------------------- 181 */ 182 mov r0, #DC_OP_CISW 183 bl dcsw_op_level1 184#endif 185 186 /* --------------------------------------------- 187 * Disable the optional ACP. 188 * --------------------------------------------- 189 */ 190 bl plat_disable_acp 191 192 /* ------------------------------------------------- 193 * Flush the L2 caches. 194 * ------------------------------------------------- 195 */ 196 mov r0, #DC_OP_CISW 197 bl dcsw_op_level2 198 199 /* --------------------------------------------- 200 * Come out of intra cluster coherency 201 * --------------------------------------------- 202 */ 203 bl cortex_a72_disable_smp 204 205 /* --------------------------------------------- 206 * Force the debug interfaces to be quiescent 207 * --------------------------------------------- 208 */ 209 pop {r12, lr} 210 b cortex_a72_disable_ext_debug 211endfunc cortex_a72_cluster_pwr_dwn 212 213declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ 214 cortex_a72_reset_func, \ 215 cortex_a72_core_pwr_dwn, \ 216 cortex_a72_cluster_pwr_dwn 217