1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <bl_common.h> 32 #include <errno.h> 33 #include <platform.h> 34 #include <plat_arm.h> 35 #include <sp805.h> 36 #include <tbbr_img_def.h> 37 #include <v2m_def.h> 38 39 #define RESET_REASON_WDOG_RESET (0x2) 40 41 void juno_reset_to_aarch32_state(void); 42 43 44 /******************************************************************************* 45 * The following function checks if Firmware update is needed, 46 * by checking if TOC in FIP image is valid or watchdog reset happened. 47 ******************************************************************************/ 48 unsigned int bl1_plat_get_next_image_id(void) 49 { 50 unsigned int *reset_flags_ptr = (unsigned int *)SSC_GPRETN; 51 unsigned int *nv_flags_ptr = (unsigned int *) 52 (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS); 53 /* 54 * Check if TOC is invalid or watchdog reset happened. 55 */ 56 if ((arm_io_is_toc_valid() != 1) || 57 ((*reset_flags_ptr & RESET_REASON_WDOG_RESET) && 58 ((*nv_flags_ptr == -EAUTH) || (*nv_flags_ptr == -ENOENT)))) 59 return NS_BL1U_IMAGE_ID; 60 61 return BL2_IMAGE_ID; 62 } 63 64 /******************************************************************************* 65 * On JUNO update the arg2 with address of SCP_BL2U image info. 66 ******************************************************************************/ 67 void bl1_plat_set_ep_info(unsigned int image_id, 68 entry_point_info_t *ep_info) 69 { 70 if (image_id == BL2U_IMAGE_ID) { 71 image_desc_t *image_desc = bl1_plat_get_image_desc(SCP_BL2U_IMAGE_ID); 72 ep_info->args.arg2 = (unsigned long)&image_desc->image_info; 73 } 74 } 75 76 /******************************************************************************* 77 * On Juno clear SYS_NVFLAGS and wait for watchdog reset. 78 ******************************************************************************/ 79 __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved) 80 { 81 unsigned int *nv_flags_clr = (unsigned int *) 82 (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR); 83 unsigned int *nv_flags_ptr = (unsigned int *) 84 (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS); 85 86 /* Clear the NV flags register. */ 87 *nv_flags_clr = *nv_flags_ptr; 88 89 while (1) 90 wfi(); 91 } 92 93 #if JUNO_AARCH32_EL3_RUNTIME 94 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 95 { 96 #if !ARM_DISABLE_TRUSTED_WDOG 97 /* Disable watchdog before leaving BL1 */ 98 sp805_stop(ARM_SP805_TWDG_BASE); 99 #endif 100 101 juno_reset_to_aarch32_state(); 102 } 103 #endif /* JUNO_AARCH32_EL3_RUNTIME */ 104